The main objective of PERLA is to develop SiGe based advanced RF building blocks for Hiperlan/2 equipment. A system company (INTRACOM), a SiGe technology provider (ST Microelectronics) and RF IC designers (SSSL and UNICT) will use concurrent engineering techniques to a SiGe technology, packaging, RF design techniques and system specification. In this way system costs will be reduced and hence permit wider application of the Hiperlan concept, thus leading to enabling technology for low cost mass market customer devices to access networked services.
A driving application toward this goal will be the development of an integrated RF transceiver chipset for Hiperlan/2 in two phases:
in Phase 1 SiGe technology will be used to replace GaAs components in an existing Hiperlan/2 prototype.
In Phase 2 the complete RF architecture will be optimised for the realisation of an integrated chipset for a lower cost frontend, which will be tested on this prototype.
The main objective of the PERLA project is to develop SiGe based advanced RF components for new generations of Hiperlan/2 equipment.
Specifically, the project aims at:
a)Replacing GaAs components in an existing Hiperlan/2 prototype system,
b)Developing techniques for using packaged SiGe devices at 5GHz,
c)Creating a design kit for a SiGe process available to outside customers,
d)Developing a novel RF integrated transceiver chipset for Hiperlan/2,
e)Developing a front-end prototype based on this chipset,
f)Disseminating the results using the appropriate channels to promote the project's results,
g)Bringing together system house/user and technology providers aiming to share their expertise and establish cooperation which should extend beyond the project's duration, creating a user-supplier partnership.
The development of an integrated transceiver chipset for Hiperlan/2 will be achieved in two phases. The first phase of the project will utilise INTRACOM's existing Hiperlan/2 prototype system and will seek to replace the GaAs components used at present with newly designed SiGe devices with a degree of integration and package innovation. In parallel, full architecture studies for further levels of integration and cost reduction will be conducted, allowing for flexibility and stability while lending itself to more efficient silicon integration, in order to lead to a second phase design and realisation. This way, the project will initially create the knowledge base required for the Phase 2 transceiver chipset and system development, thus minimising technical risks. In addition, the second generation SiGe process will be characterised and a design kit will be generated. The RF chips will be tested both standalone and at the system level on an existing Hiperlan/2 prototype which will be modified to suit the project's goals. Specifically, RF boards for Hiperlan/2 will be developed and the transceiver chipset will be placed on it. The RF subsystem will then be interfaced with the Hiperlan/2 prototype system, which currently exists to a certain degree and configuration, but it will need to be modified and adapted to interface properly with the RF subsystem. A demonstration of proper operation will be conducted at the end of the project. The results of the project will be appropriately disseminated and exploited as indicated in the exploitation plans.
- Replacement of certain GaAs components in an existing Hiperlan/2 solution.
- SiGe process enhancement, characterisation and design kit generation.
- RF transceiver and subsystem architecture.
- The development of a Hiperlan/2 transceiver chipset using state-of-the-art HBT SiGe process.
- Hiperlan/2 RF frontend subsystem.
- Modification of an existing Hiperlan/2 system, interface with developed frontend and demonstration.
Funding SchemeCSC - Cost-sharing contracts
20041 Agrate Brianza
SN1 3PR Swindon
151 25 Marousi