FLEUR main goal is to develop embedded NVM (Non Volatile Memory) devices based on ferroelectric materials and to integrate them in a single chip with CMOS logic for SMART Cards / RF ID applications. More specifically, the partners will develop a macrocell with a density of 64 Kbit, using a 2T-2C stacked cell. The array will be arranged in a 2 bytes per plate architecture to optimise the area vs. power consumption. The Workplan can be broadly divided into 4 Work packages, plus one (WP0) devoted to the Project management and dissemination.The project will require a total of about 36 Person/Years. FLEUR involves both horizontal and vertical cooperation mechanism between partners from 4 different EC member states, including two interuniversity centres, one semiconductor industry, one university department and one consumer/user industry.
FLEUR main goal is to develop embedded NVM (Non Volatile Memory) devices based on ferroelectric materials and to integrate them in a single chip with CMOS logic for SMART Cards / RF ID applications. More specifically, the partners will develop a FeRAM macrocell with a density of 64 Kbit, using a 2T-2C cell array arranged in a 2 bytes per plate architecture to optimise the area vs. power consumption. The process will be based on a 0.35 micron technology, with up to 5 levels of metallization. The ferroelectric material will be the SBT. FLEUR goals are very challenging, as they address the areas where Ferro NVMs will be needed in the next few years, with a technology platform and all other requirements making it competitive over more conventional solutions based on EEPROM cells.
DESCRIPTION OF WORK
The project duration will be two and a half years, and will require a total of about 36 Person Years. The Work plan will be divided into 5 Work Packages of which one (WP0) devoted to the Project management and dissemination, so that it will be possible to easy to identify critical paths and monitor progress. The project will be managed as a process, e.g. as series of actions leading to a result. The sequence of Work Packages has been defined according to a logical structure, where material, technology, process, design and application issues are developed and merged in dedicated phases of the work.The Workplan structure related to RTD actions is the following:WP1 Planar Ferro capacitor development: the aim is the optimisation of the fabrication technology of ferroelectric capacitors (FECAPs) for advanced NVM applications. The intention is to fabricate small, thin-film (<150 nm), planar FECAPs with high yield and uniformity, according to the final demonstrator performance.WP2 Process Integration & Contamination Issues: the objective is the integration of FECAPs and the control of the potential contamination associated with the introduction of ferroelectricsWP3 Demonstrator Design & Prototypes: the objectives are process development, cell architecture verification and test of capacitors, stacked memory cells and small memory arrays.WP4 Testing & Reliability: this work will provide feedback to WPs dealing with process and design issues.
Funding SchemeCSC - Cost-sharing contracts