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Nanoscale electronic elements and circuits for operation at room temperature

Objective

Nanoelectronics will need circuits of high level of compactness, consuming less power and operating at room temperature. We offer solutions responding to these requests, based on novel approaches recently demonstrated by members within NEAR. The discrete building blocks to be used are primarily wave-guide and point-contact devices, from which the assembly of a rich variety of functional devices and circuits is possible. Devices and circuits will be defined by a single layer nanolithography, also serving as a suitable test case for nanoimprint. Physical modelling and AC/DC-experiments on discrete nanodevices will create the input for design and implementation of circuits integrating a few nanodevice elements, such as for logic ports and/or RF-circuitry.
Nanoelectronics will need circuits of high level of compactness, consuming less power and operating at room temperature. We offer solutions responding to these requests, based on novel approaches recently demonstrated by members within NEAR. The discrete building blocks to be used are primarily wave-guide and point-contact devices, from which the assembly of a rich variety of functional devices and circuits is possible. Devices and circuits will be defined by a single layer nanolithography, also serving as a suitable test case for nanoimprint. Physical modelling and AC/DC-experiments on discrete nanodevices will create the input for design and implementation of circuits integrating a few nanodevice elements, such as for logic ports and/or RF-circuitry.

OBJECTIVES
Future applications in electronics will require a high level of compactness, low power consumption and operation at room temperature.
We offer approaches in NEAR that will deliver in response to these requests. The project partners have an established experience in the field of nanolithographic formation of geometrically defined discrete devices from a two-dimensional layer structure, primarily wave-guide and point-contact devices, from which the assembly of a rich variety of functional devices and circuits is possible. Two novel approaches towards the realization of nanoscale electronic elements and circuits for room-temperature operation have recently been proposed and demonstrated by the partners of NEAR. We will develop fabrication technologies and physical understanding as a basis for the design and implementation of functional circuits in which we will integrate few nanodevices for applications in logics as well as for RF-circuitry.

DESCRIPTION OF WORK
The competences among the partners is in:
(i) materials technology and nanoscale processing of III-V and silicon materials;
(ii) device transport physics from an experimental as well as theoretical perspective, and;
(iii) circuit design based on classical as well as quantum devices.
These areas also form the main orientations of the three workpackages (WP):
WP1: Fabrication issues involving epitaxial growth, lithography and processing, optimised for implementation in III-V as well as silicon materials. All three members in NEAR also are engaged in nanoimprint projects funded by EU, for which these devices and circuits are suitable test cases;
WP2: Discrete nanodevices, to develop experimental characterization and modelling of physical properties and parameters of discrete devices as input to circuit design. WP2 is primarily on the level of fundamental physical understanding of opportunities and limitations of the phenomena employed.
WP3: Circuit implementation integrating a few nanodevices, primarily to design, implement and study low-level integration of discrete nanodevices, with a special effort on implementation into mainstream silicon technology;
WP3 will primarily operate using standard circuit design tools (SPICE/Aplac), taking the output from the modelling based on quantum physics in WP2 as input for circuit design.
The workpackages are intended to strongly interact, with WP2 designing discrete devices and serving to evaluate technology from WP1 on the level of discrete devices. WP2 also creates the output to WP3 by delivering analytic descriptions of the performance of individual nanodevices. For implementation of circuits, integrating a few nanodevices, WP1 and WP3 are tightly interconnected.
Initially, the work will concentrate on the two new families of devices; Three Terminal Ballistic Junctions (TBJs) and Self Switching Devices (SSDs), but we believe that other nanoelectronic devices might appear that could offer additional possibilities.

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

LUNDS UNIVERSITET
Address
Paradisgatan 5C
221 00 Lund
Sweden

Participants (2)

BAYERISCHE JULIUS-MAXIMILIANS UNIVERSITAET WUERZBURG
Germany
Address
Sanderring 2
97070 Wuerzburg
VALTION TEKNILLINEN TUTKIMUSKESKUS (VTT)
Finland
Address
Vuorimiehentie 5
02044 Espoo