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Self-Aligned Single Electron Memories and Circuits

Objective

Future successful development of information technologies is strongly dependent on the continuation of Moore's law towards nano-electronics. According to the ITRS roadmap, the mainstream memory devices, e.g. DRAMs and Flash memories, will face a technological brick-wall around 2006. An ideal memory device for the coming nano-electronics era would be a silicon-technology compatible flash single-electron memory device. The aim of this project is to optimise and fabricate such nano-flash single-electron memory devices and the associated circuits using a fully MOS-compatible SOI technology. The key innovative aspects of this project rely on device design optimised for persistent operation and low voltage programming, and on a simple self-aligned SOI-MOS process. This project gathers together 3 university partners and an industrial partner interested in the high potential of this study. Future successful development of information technologies is strongly dependent on the continuation of Moore's law towards nano-electronics. According to the ITRS roadmap, the mainstream memory devices, e.g. DRAMs and Flash memories, will face a technological brick-wall around 2006. An ideal memory device for the coming nano-electronics era would be a silicon-technology compatible flash single-electron memory device. The aim of this project is to optimise and fabricate such nano-flash single-electron memory devices and the associated circuits using a fully MOS-compatible SOI technology. The key innovative aspects of this project rely on device design optimised for persistent operation and low voltage programming, and on a simple self-aligned SOI-MOS process. This project gathers together 3 university partners and an industrial partner interested in the high potential of this study.

OBJECTIVES
The critical points that currently limit performances are lithography resolution, process optimisation, and fine characterisation. The objectives of SASEM are to address these points and go from the existing laboratory single-electron-memory (SEM) device to memory circuit demonstration. In order to fully exploit the potential of our SEM device, all aspects from physics and technology to circuit architecture will be addressed. Detailed objectives: Process simulation using appropriate models for small devices and anisotropic oxidation. Device simulation and design, process optimisation for best reproducibility and robustness to process parameter fluctuations, and best device characteristics. Tests and optimisation of critical process steps. Memory device fabrication. Physical characterisation. Electrical characterisation (programming and readout, retention time). Design and fabrication of memory cells. Demonstration of a nano-flash SEM circuit.

DESCRIPTION OF WORK
The different components are grouped in the following workpackages (WP1 to WP3) and tasks. WP1: Design and simulation:
1.1 Development of specific process simulation tools that will allow device process optimisation. If necessary, 3D simulation will be considered on year 2;
1.2 Device process optimisation based on inputs from 1.1, as well as feedbacks from device characterization (3.1 and 3.3). Technological parameters will be optimised to produce the best device in terms of reproducibility and robustness to process parameter fluctuations, as well as device characteristics;
1.3 Design of a programming/readout circuit using the SOI analog circuit expertise of G1. Design improvement is based on memory cell characterization (3.4);
1.4 Design of memory circuit based on output from task 1.3. Feedback from memory circuit characterization (3.5) will drive design optimisation.

WP2: Fabrication: 2.1 Optimisation of the key process steps: lithography and oxidation. Shared by CO1 (oxidation) and CR3 (lithography). Physical characterization (3.1) will drive the present task through continuous feedbacks;
2.2 Based on inputs from tasks 1.2 and 2.1, task 2.2 is devoted to memory device fabrication. CO1 and CR3 will share process steps according to specific expertises and equipments;
2.3 Memory cell fabrication;
2.4 Memory circuit fabrication based on input from task 1.4.

WP3: Characterization;
3.1 Physical characterization using various investigation tools (SEM, AFM, FIB). Device process optimisation;
3.2 Development of specific device/circuit characterization tools to provide detailed investigation of memory device characteristics;
3.3 to 3.5: Devices, memory cells and memory circuits characterization, respectively. Provide continuous feedback to tasks 1.2, 1.3 and 1.4.

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

UNIVERSITE CATHOLIQUE DE LOUVAIN
Address
1 Place De L'universite
1348 Louvain-la-neuve
Belgium

Participants (3)

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
France
Address
3, Rue Michel-ange
75794 Paris Cedex 16
INSTITUT SUPERIEUR D'ELECTRONIQUE DU NORD
France
Address
41, Boulevard Vauban
59046 Lille
STMICROELECTRONICS SA
France
Address
29 Boulevard Romain Rolland
92120 Montrouge