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Experimental Controller for Integrated Access Devices

Objective

ECIAD is a best practise action concerning the development and adoption of skills and techniques for the design and implementation of embedded monolithic subsystems (SoC) for networking applications. The consortium consists of a system house (SME), an embedded processor core provider (SME) and a university (academia). The baseline experiment is a single chip embedded controller for integrated access devices (low cost, but rather complex customer premises equipment for Small Office - Home Office and residential networking applications). The project focuses on the efficient integration of virtual components (Intellectual property building blocks) and on the definition of an optimal design flow, where tasks not associated with partners' core competencies are appropriately outsourced.

Objectives:
The target is to augment the co-ordinator's capabilities (SME electronic systems design house) to be able to design embedded systems on a chip and to deliver H/W subsystems as "virtual components" with enhanced quality and documentation (compared to "traditional" board level subsystems).

The ECIAD project objectives are summarized as follows:
- Develop skills and procedures to generate, transfer and integrate Intellectual Property blocks for integration into VLSI (virtual components).
- Acquire technology in the area of ASIC design and prototyping;
- Optimally use the acquired technology through the revision of the company's business process;
- Carry-out the ECIAD baseline project. The baseline project is a monolithic.

Work description:
The project is decomposed in four workpackages, each addressing one group of objectives:
a. Project management (WP1);
b. Technology Adaptation and Training (WP2);
c. Baseline project implementation (WP3);
d. Dissemination and demonstration (WP4);
e. Measurement and evaluation of project results (WP5).

The workplan will lead to the following targets for the ECIAD baseline project:
a. Define the design and verification methodologies for SoC ASICs;
b. Design a basic set of IP cores, mainly concentrating on communication interfaces and functions;
c. Implementation of a complete IC subsystem using the above building blocks and the adopted processor core.

The core of the ECIAD IC is Hyperstone's E1-32XS RISC/DSP processor. The core is available as "Hard IP" in a number of digital CMOS VLSI technologies. The ECIAD virtual components are intergraded blocks of logic (and memory), with well defined interfaces and strict functionality. They will be designed based on Hardware Description Language (VHDL) and in such a way that can be used and verified in an ASIC without complete knowledge of the component's internal design and/or implementation. Given the limited resources and the constraint time-plan, it was decided to outsource the back-end steps (as part of the fabrication process). This is a relatively novel business practice, especially applicable to deep submicron (but well established) technologies. This does not alter the manufacturing strategy.

Milestones:
The baseline project will deliver:
-The ECIAD IC with embedded processor core and integrated state of the art virtual components (IP blocks) for PBX/SOHO router implementation;
-Intellectual Property (IP) blocks, developed and packaged as "virtual components";
-Ethernet (MAC layer) "thin" implementation;
-UART implementation';
-PCM interface.

Funding Scheme

ACM - Preparatory, accompanying and support measures

Coordinator

GLOBAL DIGITAL TECHNOLOGIES S.A.
Address
Eirinis Avenue 65
48100 Preveza
Greece

Participants (2)

HYPERSTONE AG
Germany
Address
Line-eid-strasse 3
78467 Konstanz
INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS
Greece
Address
Patission Street 42
10682 Athens