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Design Methodology and Environment for Dynamic RECONFigurable FPGA

Objective

The aim of RECONF2 is to allow implementation of ADAPTIVE SYSTEM ARCHITECTURES by developing a COMPLETE DESIGN ENVIRONMENT to take full benefits of dynamic reconfigurable FPGAs (D_FPGAs).

The project outputs:
- New design methodology;
- Front & Back end tools, will be validated through 3 complementary industrial experiments, covering different functions of the tools. It will help in reducing the lack of CAD/EDA activity in Europe, and will participate in the effort of standardisation. The outputs will be made widely available and will give large companies and SMEs the opportunity to develop new, complex and high performance applications.

Objectives:
The aim of RECONF2 is to develop the required design environment to be able to efficiently use dynamically reconfigurable FPGA (D_FPGA).The proposed technology will open new application opportunities, will make possible to design innovative lost cost architectures, for adaptive computing systems having to adapt permanently their algorithms to their changing environment. The main targeted application domains are: real time image processing, signal processing included in most of embedded systems, e.g. in aeronautic, automotive, multimedia, industrial process control. Although the proposed environment will be usable by all Real Time embedded systems manufacturers, it will be a unique opportunity for SMEs to access this new technology and to develop complex, high performance applications at low costs.

Work description:
The work required to achieve the project objectives has been split into 9 Work Packages (WP).

Four WPs are dedicated to the Methodology and Tool Design:
- WP2: The WP "D_FPGA & Tools Characteristics Specifications" defines the users requirements regarding the FPGA characteristics and the Design Environment requirements.
- WP3: A complete design methodology for D_FPGA is defined, including a system partitioning methodology and new design guidelines.
- WP4: Two Front-end tools are developed: A dynamic reconfiguration management tool (system partitioning) tool and a data management tool.
- WP5: Two Back-end tools are developed: a modular place&route tool and a FPGA reconfiguration tool.

Three WPs validate the Methodology and Tools on the different aspects:
- WP6: Sates Machine;
- WP7: Complex Algorithms & Real Time;
- WP8: Data Management, Test & Debug on three complementary industrial applications (space, multimedia, aeronautic).

Each WP "evaluation" is composed of the selected application detailed definition, the application design using the methodology and tools, and evaluations and feedback are provided on the methodology and tools.
The WP9 "Dissemination & Implementation" prepares for the wide acceptance of the project results and ensures their transition into the market place.
WP1 is dedicated to Project Management.

Milestones:
The project is planned over 31 months.
- At T0+3 the Users specifications, and at T0+20 the methodology, will be defined.
- Two releases of the Tools will be delivered. Intermediate versions will enable the industrial evaluations to begin early and the first feedbacks to be taken into account in the final versions.
- Mockups for evaluation will be defined at T0+15, developed at T0+30, and final evaluation reports ready at T0+31.

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

MBDA FRANCE
Address
37 Boulevard De Montmorency
75016 Paris
France

Participants (6)

ATMEL HELLAS S.A.
Greece
Address
Patras Science Park, Stadiou Str., Platani
26500 Patras
ATMEL NANTES SA
France
Address
Route De Gachet La Chantrerie
44300 Nantes
DELTATEC S.A
Belgium
Address
Rue Gilles Magnee 92/6
4430 Ans
KAYSER ITALIA S.R.L.
Italy
Address
Piazza 185 R.a. Folgore 2/3
57128 Livorno
UNIVERSITAT POLITECNICA DE CATALUNYA
Spain
Address
Jordi Girona 31
08034 Barcelona
USTAV TEORIE INFORMACE A AUTOMATIZACE - AKADEMIE VED CESKE REPUBLIKY
Czechia
Address
Pod Vodarenskou Vezi 4
182 08 Praha 8