Objective
The main objective of the ARTEMIS project is: The development of advanced module integration and device architectures for high-performance front-end CMOS technologies with limited power consumption. Target physical gate lengths range from 65 down to below 40 nm. The objectives and time line of the project have been carefully aligned to the internal roadmaps of the industrial partners in the consortium and use the most recent version of the ITRS roadmap as an overall guideline. As a result, it is expected that this project will help to increase the competitively of European companies in the semiconductors market by providing them with a technological baseline for high-performance transistors with limited power consumption with aggressive specifications in terms of gate length, junction depth and equivalent oxide thickness.
Work description:
In order to achieve the objectives, the work programme has been set up in the following manner:
- The project intends to employ the exploratory and generic work done in other past or still on-going European projects (ULTRA II, HUNT) and extend these results and the most promising solutions into mature modules;
- The scaling of process modules and transistor architectures will be pushed to their limits;
- Special emphasis will be dedicated to the implementation of advanced gate stack and junction approaches into an integrated process flow. This will allow to scale transistor gate lengths from 65 nm (at the start of the project) to below 40 nm (in the final phase of the project);
- The choice of modules will take into account the maturity of the modules for industrial use within the short time schedule for risk-production ramp up;
- The transistor architecture will be optimised in order to maximise performance and minimise leakage currents within the limitations imposed by physical and technological constraints;
- The project will focus on fabricating transistors with gate length ranging from 65 nm (at the start of the project) down to 35-40 nm (by the end of the project);
- The impact of integration choices on performance will be evaluated using test circuits (ring oscillators);
- Target specifications, benchmarking of the results obtained within the project and an outlook towards future technologies (down to 25 nm gate length by the end of the project) will be provided by means of extensive TCAD activities combined with a detailed evaluation of the state-of-the-art;
- Manufacturability and reliability aspects will receive the highest attention throughout the project in order to facilitate the posterior transfer of the results to the pre-development sites of the industrial partners.
Milestones:
The workplan is divided in different phases that correspond to the progressive scaling of device dimensions. In the first phase of the project, the baseline process developed in HUNT will be extended to 65 nm gate lengths. At M12 this phase will be finalised and work will concentrate on 45 nm devices. Finally, from M24 on, work will be focused on devices with gate lengths ranging from 35 to 40 nm. The expected result is a set of technology choices that will be used for industrial pre-development.
Fields of science (EuroSciVoc)
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
- natural sciencesphysical scienceselectromagnetism and electronicssemiconductivity
- natural sciencesphysical scienceselectromagnetism and electronicsmicroelectronics
- natural scienceschemical sciencesinorganic chemistrymetalloids
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Call for proposal
Data not availableFunding Scheme
CSC - Cost-sharing contractsCoordinator
3001 LEUVEN
Belgium