Important discoveries have enlightened a strong competitor to existing RAM which is Magnetic RAM (MRAM). Instead of using electric charges as data storage (like it is done in all kinds of RAM, even NVRAM), MRAM are using cells which magnetic state can be reversed, like in Hard Disk drives, so as to store '0' and '1' with the difference that memory is Randomly Accessed, increasing drastically data transfer rates. Based on a recent advance in the magnetism field and in order to overcome the current difficulties, the consortium will investigate two different, new, promising writing processes: the Current Induced Magnetic Switching (CIMS) and the Thermally Assisted Switching (TAS).The objective of the project is therefore to perform scientific investigation allowing either one or the other technique to result in a fully operational 1Mbit prototype which performances would be: R/W cycle < 30ns and Power consumption < 5mW for one write cycle of 256 bits.
DESCRIPTION OF WORK
In the project timeframe, the work will be divided in three actions:1. Development of materials and structures for TAS and CIMS operation with the aim of reducing the writing energy. The current density to be flowed during the writing step should be compatible with the use of magnetic tunnel junctions (MTJs). In parallel, all technological issues for the integration of the magnetic structures will be worked out: etching techniques (reactive ion etching or ion beam etching) for magnetic stack, integration of damascene interconnections with low surface roughness, cross compatibility between CMOS and magnetic tunnel junctions in terms of process conditions and temperature history.2. Demonstration of single operating cells using TAS or CIMS mode for electrical performance evaluation (R/W access time, R/W consumption, cycling). GO/ NO GO decision at month 18 according to the performance results and the integration compatibility. The selected mode will be then re-implemented for process stabilisation using the optimized technological recipes of action 1.3. Development of the memory architecture for the selected mode of operation and chip design comprising the different steps of functional design, electrical design, physical design and flow integration. Finally, the MTJ will be integrated and fully tested into a 1Mbit MRAM demonstration chip featuring targeted performances: - R/W cycle < 30ns - Optimum retention better than 10E15 R/W cycles - Power consumption < 5mW for one write cycle of 256 bits - Vwrite= 0.6V - DVread=100mV - ESD protection level to prevent MTJ from Breakdown Voltage >0.8V.
Funding SchemeCSC - Cost-sharing contracts
91830 Le Coudray Montceaux
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