To optimise the benefits from the application of process and device simulation in the semiconductor industry, European R&D in the field of simulation must follow as close as possible the requirements of industry. This requires a joint action from industry and research to derive consolidated industrial specifications and transfer them to R&D. Therefore, in the UPPER+ Working Group the state-of-the-art in the field will be assessed, detailed industrial specifications for process and device simulation will be collected, consolidated into a common set approved by leading European semiconductor companies, and disseminated to industry, government, and R&D institutes in order to contribute to the direction of future work. These actions include close interactions with existing R&D projects in the field and relevant research institutions beyond the UPPER+ consortium. UPPER+builts upon the success of the preceding User Group UPPER.
Simulation of processes and devices is regarded by industry as very important for the support of the development in microelectronics. With development costs and times being essential for industry, the importance of simulation is highlighted e.g. in the International Technology Roadmap for Semiconductors (ITRS). To optimise the benefits from simulation to the semiconductor industry sufficient R&D in the field of simulation must be carried out in time and, moreover, be directed best towards the industrial requirements. To support this, in UPPER+consolidated industrial specifications will be developed and disseminated towards related research projects and relevant research institutions. As successfully done in the preceding UPPER User Group, new related research will be promoted, and important contributions to the ITRS will be made.
The overall objective of the UPPER+ User group is to derive consolidated industrial specifications for process and device simulation, and to strongly contribute to the optimisation of European activities in the field towards their industrial benefit.
To achieve these ambitious goals, in UPPER+ the following actions will be carried out:
1) Specifications will be collected from the semiconductor companies participating in UPPER+, and from interactions with external groups;
2) A common assessment of the world-wide state-of-the-art in the field of process and device simulation will be worked out;
3) Common specifications for process and device simulation will be derived, supported by the main European semiconductor companies. These specifications will update and extend the about two year old specifications for process simulation worked out in the preceding User Group UPPER, and extend them into the field of device simulation. Whereas these will in terms of process simulation be again very detailed due to the high number and complexity of process steps, for device simulation they will focus on defining the modelling levels and approaches needed, aspects to be addressed for advanced devices, and the required model accuracy and computational efficiency. Also the institutions considered most suitable to implement the work will be identified;
4) UPPER+ will interact with existing R&D projects in the field in order to optimise their industrial use w.r.t. the UPPER+specifications;
5) Based on the specifications and the assessment of the state-of-the-art worked out in UPPER+, the consortium will promote the implementation of the UPPER+ specifications in new research projects;
6) UPPER+ will contribute to the world-wide discussion on the future requirements for semiconductor modelling and simulation by providing input to the International Technology Roadmap for Semiconductors.
The project results can be grouped according to the five main milestones: At t0+1the project WWW will be implemented, including a Call for Interaction to external groups. At t0+3, first sets of internal specifications will be collected. Att0+9, first consolidate specifications and suggestions for future research will be available. Milestones at t0+15 and t0+21 are updates and extensions of those one year earlier. Furthermore, inputs to the ITRS will be given at t0+3, t0+15,and t0+21.
Funding SchemeTHN - Thematic network contracts
20041 Agrate Brianza