Future IC technology poses challenges to the design community, mainly due to the increased integration density, power supply, and noise and error susceptibility. For the last problem, methods for fault-tolerance are being embedded. These methods are based on known error-correction codes. Initial investigations have now shown that some of the applied codes may have a potentially very advantageous effect on power consumption and noise behaviour. In view of the high benefit/cost ratio, we want to investigate these effects in a structured manner.
Investigate a recently discovered non-linear error correction technique on integrated circuit (IC) level. Particular attention will be given to expected associated benefits for chip dimensions, power consumption, simultaneous switching and signal reflections.
DESCRIPTION OF WORK
Our ambition is to achieve a Fault Tolerance coding/decoding scheme for error correction in integrated circuits, which not only corrects the errors on the chip but is also capable of tackling important issues in bus communication such as power consumption and noise. We will analyse the different electrical issues one by one to finally arrive at a complete insight and a unified approach. First we investigate the benefits of fault-tolerant coding to reduce energy consumption. Next, cross talk-effects will be investigated. Finally the effects on simultaneously switching outputs (ground bounce) will be investigated. For the latter we will focus on memories and microprocessors. This result might be applicable for worldwide standardisation. The University of Bologna is mainly doing the research to combine fault-tolerance and electrical aspects. Philips will perform modelling for the electrical aspects and provide expertise on novel fault tolerant codes. iRoC will evaluate and study the feasibility of the methods in their portfolio of fault tolerant design blocks.
Funding SchemeCSC - Cost-sharing contracts
38025 Grenoble Cedex 01