The overall objective of this project is to develop and demonstrate very high speed, 5 and 10 Gbit/s, transmission systems for various applications in the subscriber loop such as: broadcasting of TV and HDTV channels on the subscriber line, concentrator lines for switched services signals, or very high speed LANs and MANs.
The overall objectives of the research was to develop and demonstrate very high speed (5 and 10 gigabits per second) transmission systems for various applications in the subscriber loop such as:
broadcasting of television (TV) and high definition television (HDTV) channels on the subscriber line;
concentrator lines for switched services signals;
very high speed local area networks (LAN) and metropolitan area networks (MAN). Key issues were in establishing the factors limiting bit rates in subsystems and building blocks and developing viable solutions such that multiple high bit rate channel distribution becomes a practicable reality.
The research has achieved results in the following areas:
the transmission requirements for present and future services have been assessed;
various network structures for 5 gigabits per second direct detection systems have been investigated, to minimize the cost per subscriber;
the 5 gigabits per second and 10 gigabits per second demonstrators have each been specified;
chip development and layout has been completed for the first 10 gigabits per second chips.
Optical components and modules:
a list of laser diodes and photodiodes that are likely candidates for 5 gigabits per second transmitters and receivers has been complied;
the design of laser diode test fixtures has been completed;
extensive testing of 1550 nm direct feedback (DFB) lasers from direct current (DC) to 10 gigabits per second undertaken;
a 5 gigabits per second hybrid type receiver front end module has been designed and tested.
Subsystmes and demonstrators:
a 5 gigabets per second system test bed has been set up for the evaluation and optimization of electronic and optoelectronic components, modules and building blocks in a real system environment.
Starting at a bit-rate of 5 Gbit/s, components, universal building blocks and demonstrators will be realised in an evolutionary manner finally aiming at 10 Gbit/s.
With the aid of the first demonstrator, the 5 Gbit/s point-to-point link (eg HDTV feeder or TV distribution system), the usability of silicon bipolar high speed chip technologies with respect to performance and cost is analysed. 5 Gbit/s is chosen because at this intermediate bit-rate or frequency, test equipment is available and chip and laser packaging problems will not be as severe as they will be at 10 Gbit/s. The experimental results will be used especially to upgrade the parameter-set for high speed laser modelling and modelling of high speed receiver front-ends.
The final goal is to increase the bit-rate of the pure TDM system as much as possible. In a system that can carry 16 x 140 Mbit/s channels for (HD)TV signals, optical power splitters and optical amplifiers will be incorporated to demonstrate the distribution of a large number of high quality TV channels to a number of subscribers. Options for a further upgrading of the channel capacity by WDM or OTDM techniques are also analysed. The building blocks and sub-systems can later be used in many future high speed digital systems of a different nature to those actually realised as demonstrators.
The key issues are in establishing the factors limiting bit rates in the sub-systems and building blocks and developing viable solutions such that multiple high bit rate channel distribution becomes a practicable reality.
The transmission requirements for present and future services have been assessed. Various network structures for 5 Gbit/s direct detection systems have been investigated, to minimise the cost per subscriber. This included an analysis of the costs of an urban 5 Gbit/s TV distribution network and investigation of the methods for cost reduction.
The 5 Gbit/s and 10 Gbit/s demonstrators have each been specified.
Chip development and layout has been completed for the first 10 Gbit/s chips. GaAs-MESFET chips, and 5 Gbit/s silicon bipolar chips have each been fabricated.
The project has reported on WDM and OTDM applications; and contributed to CFS work (D210, D230, D740, D741, D744, D745, D770, E110, E330, E333, J100, J210, J223, J265)
Optical components and modules:
A list of laser diodes and photo-diodes that are likely candidates for 5 Gbit/s transmitters and receivers has been complied. The design of laser diode test fixtures has been completed, and extensive testing of 1550 nm DFB lasers from DC to 10 Gbit/s undertaken.
Commercially available DFB lasers have been compared with lasers delivered by other RACE projects, eg AQUA, and in-house lasers of R1051 project partners. The small-signal equivalent circuits for these have been measured, and their behaviour simulated, together with a laser driver.
A 5 Gbit/s hybrid type receiver front-end module has been designed and tested.
Sub-systems and demonstrators:
A 5 Gbit/s system testbed has been set up for the evaluation and optimisation of electronic and opto- electronic components, modules and building blocks in a real system environment
A system experiment demonstrating the distribution of 64 (HD)TV channels coded at 140 Mbit/s (total bitrate 8.96 Gbit/s) to 262 144 subscribers using an optical distribution network with optical amplifiers has been carried out. The system was shown in operation at the ECOC'91 exhibition in Paris.
Once the concept of universal building blocks operating at very high bit-rates is a practical reality, then the performance of the broadband CAC and other networks can be enhanced in a cost effective fashion leading to greater flexibility for the IBC.