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ERror-free CLAdded PHOtonic circuits

Objective

Today’s nanometer-scale imprecision in the fabrication of Photonic Integrated Circuits (PICs) induce optical phase errors, with multiple negative consequences. Current error mitigation techniques negatively impact PICs energy budget, PICs complexity, PICs costs and more broadly PICs potential to scale-up. ERCLAPHO’s aim is to establish a new technique for permanently correcting these fabrication errors in cladded PICs, with the following assets: the technique is non-volatile, is specific, it imparts no optical loss, it reaches picometer wavelength precision, and it is scalable.

ERCLAPHO starts from a patented technology discovered along ERC research projects, and now validated on uncladded PICs made out of silicon materials and III-V semiconductors. ERCLAPHO will adapt this technology to cladded Photonic Integrated Circuits, which constitute the largest industrial stake today, and where no fully satisfying solution exists. Two developments will be pursued in parallel along the project, aiming at tuning (correcting) the PIC before or after the cladding deposition. The RD effort will be carried in link with mid-scale foundry partners, in order to remain close to production constraints and facilitate the technology transfer. By building a case with these first ecosystem partners, ERCLAPHO ambitions to come closer to the requirements of large-scale production foundries.

Fields of science (EuroSciVoc)

Programme(s)

Topic(s)

Funding Scheme

HORIZON-ERC-POC - HORIZON ERC Proof of Concept Grants

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Call for proposal

(opens in new window) ERC-2026-POC

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Host institution

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS
Net EU contribution
€ 150 000,00
Address
RUE MICHEL ANGE 3
75794 Paris
France
Region
Ile-de-France Ile-de-France Paris
Activity type
Research Organisations
Links
Total cost
No data

Beneficiaries (1)