Objective Today, the JLP project is focussing on the development and qualification of a state-of-the-art CMOS process with a feature size of 0.5 microns and on analog and low-voltage options in the 0.7 micron technology generation. These processes are targeted on a very broad range of applications (including high-performance digital logic circuits as found in consumer and computer products, and low-power and low-voltage chips for use in portable equipment), as well as having the capability to combine analogue functions typically used in the telecommunication and automotive sectors of the market.In the initial phase, the emphasis was on the development of a core 0.7 micron complementary metal oxide semiconductor (CMOS) technology and on functional options (nonvolatile memories, analogue) in a 1 micron technology. The project is concentrating on the development and qualification of a state of the art CMOS process with a feature size of 0.5 microns and on analogue and low voltage options in the 0.7 micron technology generation. These processes are targeted on a very broad range of applications (including high performance digital logic circuits as found in consumer and computer products, and low power and low voltage chips for use in portable chips for use in portable equipment), as well as having the capability to combine analogue functions typically used in the telecommunication and automotive sectors of the market. The project generates the basic 0.5 micron CMOS technology by the joint effort of the partners in a subproject dedicated to the development of the basic process steps; develops various functional options to be added to the core process (activities on analogue and low voltage are organized in 2 separate subprojects); integrates the core technologies into processes for specific exploitation area and demonstrates and qualifies the technology by means of several company specific demonstrators.The JESSI JLP is one of the projects proposed in 1991 and 1993 by the JESSI organisation for Community funding. The project has already been funded for the 18 month start-up-phase of JESSI during 1990-91 (project 5080), and also incorporates the activities of project 5048 (ACCESS). For the main phase of JESSI, which started in 1992, the consortia have proposed a three-year project which combines the resources of the eight major European semiconductor companies and two of the leading research institutes. According to Dataquest, these companies together took a 9.1% share of the world semiconductor market in 1991. In JESSI, being a set of project clusters which together tackle not only the development of key process technologies but also the development of the manufacturing equipment and applications, the Joint Logic project occupies a central position as it is strongly connected and to a large extent driven by the user-defined applications projects (known as "Europrojects"). The timetable of the project has been coordinated with the technology requirements of these key applications drivers, and in particular with the "Mobile Radio", "Broadband Communications", "HDTV", "Digital Audio Broadcasting", and "Automotive Safety Electronics" activities. The partners in these latter projects are funded by their respective national governments in the context of the EUREKA programme. The JLP project also guides the work undertaken by European R&D centres on next-generation 0.25 micron CMOS technology (project 7236/8002). Fields of science natural scienceschemical sciencesinorganic chemistryinorganic compoundsengineering and technologymechanical engineeringvehicle engineeringautomotive engineeringnatural sciencesphysical scienceselectromagnetism and electronicssemiconductivityengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technologymobile radio Programme(s) FP3-ESPRIT 3 - Specific research and technological development programme (EEC) in the field of information technologies, 1990-1994 Topic(s) Data not available Call for proposal Data not available Funding Scheme Data not available Coordinator PHILIPS INTERNATIONAL BV EU contribution No data Address GERSTWEG, 2 6534 AE NIJMEGEN Netherlands See on map Total cost No data Participants (9) Sort alphabetically Sort by EU Contribution Expand all Collapse all CNET-SEPT France EU contribution No data Address 42 RUE DES COUTURES 14066 CAEN See on map Total cost No data EUROPEAN SILICON STRUCTURES S.A. France EU contribution No data Address ZONE INDUSTRIELLE 13106 ROUSSET See on map Total cost No data GEC Plessey Semiconductors plc United Kingdom EU contribution No data Address Cheney Manor SN2 2QW Swindon See on map Total cost No data INTERUNIVERSITAIR MIKROELEKTRONICA CENTRUM Belgium EU contribution No data Address KAPELDREEF, 75 3030 HEVERLEE See on map Total cost No data MATRA-MHS France EU contribution No data Address 3008 ROUTE DE GACHET 44087 NANTES See on map Total cost No data MIETEC Belgium EU contribution No data Address WESTERRING, 15 9700 OUDENAARDE See on map Total cost No data Siemens AG Germany EU contribution No data Address Otto-Hahn-Ring 6 81739 München See on map Total cost No data Telefunken Microelectronic GmbH Germany EU contribution No data Address Theresienstraße 2 74072 Heilbronn See on map Total cost No data Thomson Microelectronics Srl (SGS) Italy EU contribution No data Address Via Carlo Olivetti 20041 Agrate Brianza Milano See on map Total cost No data