Community Research and Development Information Service - CORDIS

H2020

MOS-QUITO Report Summary

Project ID: 688539
Funded under: H2020-EU.2.1.1.

Periodic Reporting for period 1 - MOS-QUITO (MOS-based Quantum Information TechnOlogy)

Reporting period: 2016-04-01 to 2017-09-30

Summary of the context and overall objectives of the project

This project is positioned in the most forefront area of Information and Communication Technology, where new computing paradigms are targeted. Here we deal with the revolutionary concept of quantum computation. We propose to take one of the most promising approaches to quantum computing and implement it onto an industrial CMOS platform. Within the three-year timeframe of this project, we can accomplish the first important step of this implementation: the realisation of the first CMOS-based spin qubit, the basic building block of a quantum computer. To this aim, we are taking advantage of a state-of-the-art silicon-on-insulator technology available at the 300-mm CMOS platform of CEA-LETI. A variety of spin qubits in silicon have already been proposed and experimentally demonstrated in academic research laboratories. The central aim of this project is to show that such high-fidelity spin qubits can be manufactured in silicon using industry-standard CMOS processes within a large-scale nanofabrication facility. Our approach is based one a single, versatile building block, which can be tuned to operate in different regimes giving up to five different qubit realisations in one device (see Fig. 1). The performance of these different qubits will be benchmarked against key criteria such as fidelity, speed and suitability for large-scale integration.
Design and modelling will be used alongside measured performance metrics to identify optimal large-scale architectures, while control tools will be developed which can be applied to scaled qubit arrays. In addition, we shall develop a toolkit of CMOS-based, classical devices (low-noise amplifiers, rf generators and multiplexers) to be used as low-temperature peripheral electronics for improved qubit control and readout. By sharing the same CMOS technology, qubits and peripheral electronics could even lie close to each other on the same chip. This unique opportunity could be particularly helpful in the development of fast readout circuitry.
Summary of the main goals and related work packages (WPs):
• Fabricate spin qubit devices using 300-mm SOI technology (WP 2)
• Implement and compare different qubit schemes (WP 3 & 5)
• Optimize qubit design for large-scale integration (WP 3 & 5)
• Develop a quantum control toolbox suitable for large-scale integrated qubits (WP4)
• Develop low-temperature peripheral electronics for improved qubit control (WP6)

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

Main actions and results in the first 18 months:

WP2 focused mostly on device fabrication, with a core fabrication line, relying on the 300-mm CMOS cleanroom of CEA-LETI, and a complementary line relying on more versatile, smaller-scale cleanrooms available at VTT, UCPH, and CEA. CEA-LETI delivered a first set of 300-mm wafers containing silicon nanowire MOSFET devices with up to four gates. The fabrication of these devices was funded through earlier projects, including EU projects SiAM and TOLOP. The devices were pre-screened by CEA at room temperature and then shared with the other MOS-QUITO partners for low-temperature experiments down to 10mK, as discussed in WP3 and WP4. Following input from all the partners in the consortium, CEA-LETI and VTT designed dedicated mask sets for both MOS-based qubits and cryo-CMOS electronics. Device fabrication is currently ongoing and delivery of the first processed wafers is expected in January-March 2018.

WP3 focused on the study of single, double, and quadruple gate devices fabricated in the CEA 300-mm fab line. These devices were produced in the SiAM and TOLOP projects. CEA reported the first electrically controlled hole spin qubit issued from a CMOS fab line. CEA, UCPH, HIT, UCL, and CNR explored and demonstrated the tunability of MOS-type silicon nanowire devices to a few-electron regime suitable for qubit operation. HIT demonstrated a reconfigurable quadruple quantum dots in four-gate transistors with double split-gate geometry. These studies were predominantly based on low-temperature electron transport measurements. In parallel to that, all partners in WP3 worked on the development/upgrade of their cryogenic setups in the prospect of implementing RF techniques for spin qubit manipulation and readout. In particular, HIT, UCL, UCPH, and CEA performed measurements of inter-dot tunneling (including coherent charge oscillations, HIT&UCL) though RF gate reflectometry, which is a first step towards the implementation of reflectometry-based spin readout.

WP4 focused on developing techniques to achieve and optimize spin manipulation, with a particular focus on methods which will scale up to large arrays of spin qubits. Our approach is to explore several options for scalable control, including AC magnetic fields for direct coupling to spins, or AC electric fields which couple to spins via an intrinsic or effective spin-orbit coupling. UCL has designed and successfully tested 3D microwave cavities for spin control meditated by a global AC magnetic field. UCL also designed and fabricated microwave striplines over silicon nanowire devices from CEA-LETI for a local, on-chip generation of the AC magnetic field. CEA made excellent progress in the demonstration and study of coherent electric field driving of hole-based spin qubits in CEA-LETI’s devices. In addition, CEA discovered a new route for electric-field-driven spin resonance which could be applied to electron spin qubits in silicon. This approach relies of valley-mediated spin-orbit coupling.

WP5 focused on a variety of activities with different goals: i) CNR Studied and benchmarked 3 of the 5 qubit implementations envisioned in MOS-QUITO: single-electron spin qubit, singlet-triplet qubit, and the so-called hybrid qubit using three electrons in a two dots. The effect of different noise sources on qubit manipulation was addressed. ii) UCPH simulated ferromagnetic microstructures for integration with Si qubits, providing guidance for fabrication at VTT. iii) CEA-INAC developed tools for the multi-scale modeling of silicon qubits, and explored opportunities for an “all-electrical” manipulation of electron and hole spins, establishing the conditions for using the Electric Dipole Spin Resonance mechanism for robust spin manipulation. We have also started to investigate the impact of device scaling on qubit properties.

WP6 progressed along two axes: i) EPFL measured and modeled MOSFETs based on 28-nm bulk CMOS down to 4 K. The

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

In the first 18-month period, the MOS-QUITO project has accomplished significantly innovative results including the first demonstration of a silicon spin qubit issued from an industry-standard fab line. This result has attracted considerable interest, in particular from the microelectronic engineering community.

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