European Exascale System Interconnect and Storage

Project Information

ExaNeSt

Grant agreement ID: 671553

DOI 10.3030/671553

Project closed

EC signature date 29 June 2015

Start date 1 December 2015

End date 31 May 2019

Funded under

• EXCELLENT SCIENCE - Future and Emerging Technologies (FET)

Total cost € 8 442 547,50

EU contribution € 8 442 547,50

Coordinated by

IDRYMA TECHNOLOGIAS KAI EREVNAS
Greece

Deliverables

Documents, reports (8)

Requirement analysis (network and storage) and Porting Roadmap

This deliverable will include the results from the analysis of the beneficiaries' applications in terms of performance, communication and power requirements. Moreover based on this analysis, this deliverable will report the essential system attributes and requirements that the ExaNeSt framework should provide. Finally this deliverable will provide the porting strategy and roadmap.

New node technologies and exascale systems

This deliverable will investigate the functionality and performance of the EUROSERVER Compute Node or other high-performance Compute Nodes in the ExaNeSt infrastructrure.

Final report on the validated and optimized storage and data access infrastructure

This deliverable will provide the final report on the validated and optimized storage and data access infrastructure.

Census of the applications

This deliverable is report that descibes the HPC applications that they will be used for the evaluation of the ExaNeSt platform.

Final recommendation and future work

This deliverable will provide recommentations on the network and storage architecture based on the evaluation of the ExaNeSt platform. Moreover it will provide future plans and work that will be performed after the end of the project.

Preliminary Dissemination report

This deliverable will provide a report describing the preliminiary dissemination and communication actions.

Final Dissemination report

This deliverable will provide a report describing the final dissemination and communication actions.

Intermediate Dissemination report

This deliverable will provide a report describing the intermediate dissemination and communication actions.

Other (1)

Implementation notes for the storage and data access infrastructure

This deliverable will describe the implementation of the software components and tools for the HPC storage and data access infrstructure specified in D4.1.

Publications

Peer reviewed articles (12)

An Optimal Single-Path Routing Algorithm in the Datacenter Network DPillar

Author(s): Alejandro Erickson, Abbas E. Kiasari, Javier Navaridas, Iain A. Stewart
Published in: IEEE Transactions on Parallel and Distributed Systems, Issue 28/3, 2017, Page(s) 689-703, ISSN 1045-9219
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TPDS.2016.2591011

The stellar transformation: From interconnection networks to datacenter networks

Author(s): Alejandro Erickson, Iain A. Stewart, Javier Navaridas, Abbas E. Kiasari
Published in: Computer Networks, Issue 113, 2017, Page(s) 29-45, ISSN 1389-1286
Publisher: Elsevier BV
DOI: 10.1016/j.comnet.2016.12.001

Efficient Sharing of Optical Resources in Low-Power Optical Networks-on-Chip

Author(s): Sebastian Werner, Javier Navaridas, Mikel Luján
Published in: Journal of Optical Communications and Networking, Issue 9/5, 2017, Page(s) 364, ISSN 1943-0620
Publisher: Optical Society of America
DOI: 10.1364/jocn.9.000364

A Survey on Optical Network-on-Chip Architectures

Author(s): Sebastian Werner, Javier Navaridas, Mikel Luján
Published in: ACM Computing Surveys, Issue 50/6, 2018, Page(s) 1-37, ISSN 0360-0300
Publisher: Association for Computing Machinary, Inc.
DOI: 10.1145/3131346

Improved routing algorithms in the dual-port datacenter networks HCN and BCN

Author(s): Alejandro Erickson, Iain A. Stewart, Jose A. Pascual, Javier Navaridas
Published in: Future Generation Computer Systems, Issue 75, 2017, Page(s) 58-71, ISSN 0167-739X
Publisher: Elsevier BV
DOI: 10.1016/j.future.2017.05.004

INRFlow: An interconnection networks research flow-level simulation framework

Author(s): Javier Navaridas, Jose A. Pascual, Alejandro Erickson, Iain A. Stewart, Mikel Luján
Published in: Journal of Parallel and Distributed Computing, Issue 130, 2019, Page(s) 140-152, ISSN 0743-7315
Publisher: Academic Press
DOI: 10.1016/j.jpdc.2019.03.013

Enabling shared memory communication in networks of MPSoCs

Author(s): Joshua Lant, Caroline Concatto, Andrew Attwood, Jose A. Pascual, Mike Ashworth, Javier Navaridas, Mikel Luján, John Goodacre
Published in: Concurrency and Computation: Practice and Experience, 2018, Page(s) e4774, ISSN 1532-0626
Publisher: John Wiley & Sons Inc.
DOI: 10.1002/cpe.4774

On the effects of allocation strategies for exascale computing systems with distributed storage and unified interconnects

Author(s): Jose A. Pascual, Joshua Lant, Caroline Concatto, Andrew Attwood, Javier Navaridas, Mikel Luján, John Goodacre
Published in: Concurrency and Computation: Practice and Experience, 2018, Page(s) e4784, ISSN 1532-0626
Publisher: John Wiley & Sons Inc.
DOI: 10.1002/cpe.4784

On-chip wireless silicon photonics: from reconfigurable interconnects to lab-on-chip devices

Author(s): Carlos García-Meca, Sergio Lechago, Antoine Brimont, Amadeu Griol, Sara Mas, Luis Sánchez, Laurent Bellieres, Nuria S Losilla, Javier Martí
Published in: Light: Science & Applications, Issue 6/9, 2017, Page(s) e17053-e17053, ISSN 2047-7538
Publisher: Nature
DOI: 10.1038/lsa.2017.53

Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development

Author(s): Manolis Katevenis, Roberto Ammendola, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Piero Vicini, Giuliano Taffoni, Jose A. Pascual, Javier Navaridas, Mikel Luján, John Goodacre, Bernd Lietzow, Angelos Mouzakitis, Nikolaos Chrysos, Manolis Marazakis, Paolo Gorlani, Stefano
Published in: Microprocessors and Microsystems, Issue 61, 2018, Page(s) 58-71, ISSN 0141-9331
Publisher: Elsevier BV
DOI: 10.1016/j.micpro.2018.05.009

Modeling and analysis of the performance of exascale photonic networks

Author(s): José Duro, Jose A. Pascual, Salvador Petit, Julio Sahuquillo, María E. Gómez
Published in: Concurrency and Computation: Practice and Experience, 2019, Page(s) e4773, ISSN 1532-0626
Publisher: John Wiley & Sons Inc.
DOI: 10.1002/cpe.4773

Iris

Author(s): Anastasios Papagiannis, Giorgos Saloustros, Manolis Marazakis, Angelos Bilas
Published in: ACM SIGOPS Operating Systems Review, Issue 50/1, 2017, Page(s) 3-11, ISSN 0163-5980
Publisher: ACM
DOI: 10.1145/3041710.3041713

Book chapters (5)

Receive-Side Notification for Enhanced RDMA in FPGA Based Networks

Author(s): Joshua Lant, Andrew Attwood, Javier Navaridas, Mikel Lujan, John Goodacre
Published in: Architecture of Computing Systems – ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings, Issue 11479, 2019, Page(s) 224-235, ISBN 978-3-030-18655-5
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-18656-2_17

On the Effects of Data-Aware Allocation on Fully Distributed Storage Systems for Exascale

Author(s): Jose A. Pascual, Caroline Concatto, Joshua Lant, Javier Navaridas
Published in: Euro-Par 2017: Parallel Processing Workshops - Euro-Par 2017 International Workshops, Santiago de Compostela, Spain, August 28-29, 2017, Revised Selected Papers, Issue 10659, 2018, Page(s) 725-736, ISBN 978-3-319-75177-1
Publisher: Springer International Publishing
DOI: 10.1007/978-3-319-75178-8_58

A CAM-Free Exascalable HPC Router for Low-Energy Communications

Author(s): Caroline Concatto, Jose A. Pascual, Javier Navaridas, Joshua Lant, Andrew Attwood, Mikel Lujan, John Goodacre
Published in: Architecture of Computing Systems – ARCS 2018, Issue 10793, 2018, Page(s) 99-111, ISBN 978-3-319-77609-5
Publisher: Springer International Publishing
DOI: 10.1007/978-3-319-77610-1_8

Direct N-body Code on Low-Power Embedded ARM GPUs

Author(s): David Goz, Sara Bertocco, Luca Tornatore, Giuliano Taffoni
Published in: Intelligent Computing - Proceedings of the 2019 Computing Conference, Volume 1, Issue 997, 2019, Page(s) 179-193, ISBN 978-3-030-22870-5
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-22871-2_14

The brain on low power architectures: Efficient simulation of cortical slow waves and asynchronous states

Author(s): R. Ammendola, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, L. Pontisso, F. Simula, P. Vicini
Published in: Advances in Parallel Computing, Issue Vol. 32, 2018, Page(s) 760-769
Publisher: IOS Press
DOI: 10.3233/978-1-61499-843-3-760

Conference proceedings (19)

Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links

Author(s): Sebastian Werner, Javier Navaridas, Mikel Lujan
Published in: 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, Page(s) 265-276, ISBN 978-1-5090-4985-1
Publisher: IEEE
DOI: 10.1109/hpca.2017.23

Network-on-chip evaluation for a novel neural architecture

Author(s): Markos Kynigos, Javier Navaridas, Luis A. Plana, Steve Furber
Published in: Proceedings of the 15th ACM International Conference on Computing Frontiers - CF '18, 2018, Page(s) 216-219, ISBN 9781-450357616
Publisher: ACM Press
DOI: 10.1145/3203217.3203268

Subchannel Scheduling for Shared Optical On-chip Buses

Author(s): Sebastian Werner, Javier Navaridas, Mikel Lujan
Published in: 2017 IEEE 25th Annual Symposium on High-Performance Interconnects (HOTI), 2017, Page(s) 49-56, ISBN 978-1-5386-1013-8
Publisher: IEEE
DOI: 10.1109/hoti.2017.18

High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings

Author(s): Jose A. Pascual, Javier Navaridas
Published in: Proceedings of the 2018 International Conference on Supercomputing - ICS '18, 2018, Page(s) 129-138, ISBN 9781-450357838
Publisher: ACM Press
DOI: 10.1145/3205289.3205307

Design Exploration of Multi-tier interconnection networks s for Exascale systems

Author(s): Navaridas, J., Lant, J., Pascual Saiz, J., Luján, M., & Goodacre, A.
Published in: ICPP 2019 : International Conference on Parallel Processing, 2019, Page(s) TBD
Publisher: ACM

Scalability of a Silicon Photonic Switch for High Performance Interconnects

Author(s): M. Kynigos, J. Navaridas and J.A. Pascual
Published in: Emit, 2019
Publisher: Emit

Direct Communications between Disributed FPGA

Author(s): J. Lant, J. Navaridas
Published in: Emit, 2019
Publisher: Emit

Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems

Author(s): Francesco Simula, Elena Pastorelli, Pier Stanislao Paolucci, Michele Martinelli, Alessandro Lonardo, Andrea Biagioni, Cristiano Capone, Fabrizio Capuani, Paolo Cretaro, Giulia De Bonis, Francesca Lo Cicero, Luca Pontisso, Piero Vicini, Roberto Ammendola
Published in: 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2019, Page(s) 283-290, ISBN 978-1-7281-1644-0
Publisher: IEEE
DOI: 10.1109/empdp.2019.8671627

Accurate Congestion Control for RDMA Transfers

Author(s): Dimitris Giannopoulos, Nikos Chrysos, Evangelos Mageiropoulos, Giannis Vardas, Leandros Tzanakis, Manolis Katevenis
Published in: 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018, Page(s) 1-8, ISBN 978-1-5386-4893-3
Publisher: IEEE
DOI: 10.1109/nocs.2018.8512155

Gaussian and Exponential Lateral Connectivity on Distributed Spiking Neural Network Simulation

Author(s): Elena Pastorelli, Pier Stanislao Paolucci, Francesco Simula, Andrea Biagioni, Fabrizio Capuani, Paolo Cretaro, Giulia De Bonis, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Luca Pontisso, Piero Vicini, Roberto Ammendola
Published in: 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), 2018, Page(s) 658-665, ISBN 978-1-5386-4975-6
Publisher: IEEE
DOI: 10.1109/pdp2018.2018.00110

An Efficient Memory-Mapped Key-Value Store for Flash Storage

Author(s): Anastasios Papagiannis, Giorgos Saloustros, Pilar González-Férez, Angelos Bilas
Published in: Proceedings of the ACM Symposium on Cloud Computing - SoCC '18, 2018, Page(s) 490-502, ISBN 9781-450360111
Publisher: ACM Press
DOI: 10.1145/3267809.3267824

Workload Characterization for Exascale Computing Networks

Author(s): Jose Duro, Salvador Petit, Julio Sahuquillo, Maria Gomez
Published in: 2018 International Conference on High Performance Computing & Simulation (HPCS), 2018, Page(s) 383-389, ISBN 978-1-5386-7879-4
Publisher: IEEE
DOI: 10.1109/hpcs.2018.00069

The next Generation of Exascale-class Systems: the ExaNeSt Project

Author(s): R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero, A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Simula, P. Vicini, G. Taffoni, John Goodacree, Mikel Lujn, J. Navaridas, J. P. Saiz, N. Chrysos, and M. Katevenis for the ExaNeSt team
Published in: Euromicro Conference on Digital System Design (DSD 2017), 2017
Publisher: IEEE
DOI: 10.5281/zenodo.823595

The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems

Author(s): M. Katevenis, N. Chrysos, M. Marazakis, I. Mavroidis, F. Chaix, N. Kallimanis, J. Navaridas, J. Goodacre, P. Vicini, A. Biagioni, P. S. Paolucci, A. Lonardo, E. Pastorelli, F. Lo Cicero, R. Ammendola, P. Hopton, P. Coates, G. Taffoni, S. Cozzini, M. Kersten, Y. Zhang, J. Sahuquillo, S. Lechago, C. Pinto, B. Lietzow, D. Everett, G. Perna
Published in: 2016 Euromicro Conference on Digital System Design (DSD), 2016, Page(s) 60-67, ISBN 978-1-5090-2817-7
Publisher: IEEE
DOI: 10.1109/DSD.2016.106

Modeling a Photonic Network for Exascale Computing

Author(s): Jose Duro, Salvador Petit, Julio Sahuquillo and Maria E. Gomez
Published in: 3rd International Workshop on Modeling and Simulation of Parallel and Distributed Systems (MSPDS 2017), 2017
Publisher: IEEE
DOI: 10.5281/zenodo.823624

Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework

Author(s): Jose Puche, Sergio Lechago, Salvador Petit, María E. Gómez and Julio Sahuquillo
Published in: Workshop on Modeling and Simulation of Parallel and Distributed Systems, 2016
Publisher: IEEE
DOI: 10.5281/zenodo.804004

Designing an exascale interconnect using multi-objective optimization

Author(s): Jose A. Pascual, Joshua Lant, Andrew Attwood, Caroline Concatto, Javier Navaridas, Mikel Lujan, John Goodacre
Published in: 2017 IEEE Congress on Evolutionary Computation (CEC), 2017, Page(s) 2209-2216, ISBN 978-1-5090-4601-0
Publisher: IEEE
DOI: 10.1109/CEC.2017.7969572

User-space I/O for μs-level storage devices

Author(s): Anastasios Papagiannis, Giorgos Saloustros, Manolis Marazakis, Angelos Bilas
Published in: Michela Taufer, Bernd Mohr, Julian M. Kunkel (Eds.): High Performance Computing, LNCS 9945, ISC High Performance 2016 International Workshops ExaComm, E-MuCoCoS, HPC-IODC, IXPUG, IWOPH, P3MA, VHPC, WOPSSS, Issue LNCS 9945, 2016, Page(s) 638-648, ISBN 978-3-319-46078-9
Publisher: Springer International Publishing
DOI: 10.1007/978-3-319-46079-6_44

Lightweight and Generic RDMA Engine Para-virtualization for the KVM Hypervisor

Author(s): Angelos Mouzakitis, Christian Pinto, Nikolay Nikolaev, Alvise Rigo, Daniel Raho, Babis Aronis, Manolis Marazakis
Published in: 2017 International Conference on High Performance Computing & Simulation (HPCS 2017), 2017
Publisher: IEEE
DOI: 10.5281/zenodo.807607

Non-peer reviewed articles (3)

Virtualized Multi-Channel RDMAwith Software-Defined Scheduling

Author(s): Kyriakos Paraskevas, Nikolaos Chrysos, Vassilis Papaefstathiou, Pantelis Xirouchakis, Panagiotis Peristerakis, Michalis Giannioudis, Manolis Katevenis
Published in: Procedia Computer Science, Issue 136, 2018, Page(s) 82-90, ISSN 1877-0509
Publisher: Science Direct
DOI: 10.1016/j.procs.2018.08.240

High signal-to-noise ratio ultra-compact lab-on-a-chip microflow cytometer enabled by silicon optical antennas

Author(s): Sergio Lechago, Carlos García-Meca, Nuria Sánchez-Losilla, Amadeu Griol, Javier Martí
Published in: Optics Express, Issue 26/20, 2018, Page(s) 25645, ISSN 1094-4087
Publisher: Optical Society of America
DOI: 10.1364/oe.26.025645

Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project

Author(s): R Ammendola, A Biagioni, P Cretaro, O Frezza, F Lo Cicero, A Lonardo, M Martinelli, P S Paolucci, E Pastorelli, F Pisani, F Simula, P Vicini, J Navaridas, F Chaix, N Chrysos, M Katevenis, V Papaeustathiou
Published in: Journal of Physics: Conference Series, Issue 898, 2017, Page(s) 082045, ISSN 1742-6588
Publisher: Institute of Physics
DOI: 10.1088/1742-6596/898/8/082045

Other (8)

Large scale low power computing system: status of network design in ExaNeSt and EuroEXA projects

Author(s): R. Ammendola, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, L. Pontissio, F. Simula and P. Vicini
Published in: Advances in Parallel Computing, 2018
Publisher: IEEE
DOI: 10.3233/978-1-61499-843-3-750

Enabling Standalone FPGA Computing

Author(s): J. Lant, J. Navaridas, A. Attwood, M. Lujan and J. Goodacre
Published in: IEEE Symposium on High Performance Interconnects, 2019
Publisher: IEEE

Direct N-body code designed for cluster based on heterogeneous computational nodes

Author(s): D. Goz, L. Tornatore, S. Bertocco & G. Taffoni
Published in: INAF-OATS Technical Report, 2018
Publisher: INAF
DOI: 10.20371/inaf/pub/2018_00005

Direct N-Body code designed for heterogeneous platforms

Author(s): D. Goz, S. Bertocco, L. Tornatore, G. Taffoni
Published in: INAF, 2018
Publisher: INAF
DOI: 10.20371/inaf/pub/2018_00002

Software and Hardware co-design for low power HPC Platforms

Author(s): M. Ploumidis, N.D. Kallimanis, M. Asiminakis, N. Chryos, P. Xirouchakis, M. Gianoudis, L. Tzanakis, N. Dimou, A. Psistakis, P. Peristerkis, G. Kalokairinos, V. Papaefstathiou and M. Katevenis
Published in: Exacomm, 2019
Publisher: Exacomm

Enabling Standalone FPGA Computing

Author(s): Joshua Lant, Javier Navaridas, Andrew Attwood, Mikel Lujan and John Goodacre
Published in: IEEE Micro, 2019
Publisher: IEEE

Performance of direct N-body code on ARM64 SoC

Author(s): D. Goz, L. Tornatore, S. Bertocco & G. Taffoni
Published in: INAF-OATS Technical Report, 2018
Publisher: INAF
DOI: 10.20371/inaf/pub/2018_00006

Distributed Processing and Transaction Replication in MonetDB - Towards a Scalable Analytical Database System in the Cloud

Author(s): Ying Zhang, Dimitar Nedev, Panagiotis Koutsourakis, and Martin Kersten
Published in: Final Public Workshop from LeanBigData and CoherentPaaS, 2016
Publisher: n/a
DOI: 10.5281/zenodo.803988

Intellectual Property Rights

Patent (11)

Pumped Primary Coolant

Application/Publication number: 1 619987.9
Date: 2016-11-25
Applicant(s): ICEOTOPE RESEARCH & DEVELOPMENT LTD

Expanding Thermal Bus

Application/Publication number: GB 1613234.2
Date: 2016-09-14
Applicant(s): ICEOTOPE RESEARCH & DEVELOPMENT LTD

Closed Loop Mains Water Control

Application/Publication number: GB 1621085.8
Date: 2017-11-27
Applicant(s): ICEOTOPE RESEARCH & DEVELOPMENT LTD

Dynamic Max-Min Fair Rate Regulation Apparatuses, Methods, and Systems

Application/Publication number: US 2016/0087899 A1
Date: 2015-09-24

Power Supply Bath

Application/Publication number: GB 1714313.2
Date: 2017-09-06
Applicant(s): ICEOTOPE RESEARCH & DEVELOPMENT LTD

AN IMMERSION COOLING SYSTEM

Application/Publication number: EP 16777786
Date: 2016-10-03
Applicant(s): ICEOTOPE RESEARCH & DEVELOPMENT LTD

Dynamic Max-Min Fair Rate Regulation Apparatuses, Methods, and Systems

Application/Publication number: US 2016/0087899 A1
Date: 2015-09-24

I/O Board

Application/Publication number: 1 619976.2
Date: 2016-11-25
Applicant(s): ICEOTOPE RESEARCH & DEVELOPMENT LTD

Pumped Primary Coolant

Application/Publication number: 1 619987.9
Date: 2016-11-25
Applicant(s): ICEOTOPE RESEARCH & DEVELOPMENT LTD

Coolant Delivery Nozzle

Application/Publication number: GB 1714308.2
Date: 2017-09-06
Applicant(s): ICEOTOPE RESEARCH & DEVELOPMENT LTD

I/O Board

Application/Publication number: 1 619976.2
Date: 2016-11-25
Applicant(s): ICEOTOPE RESEARCH & DEVELOPMENT LTD