European Exascale System Interconnect and Storage

Risultati finali

Requirement analysis (network and storage) and Porting Roadmap

This deliverable will include the results from the analysis of the beneficiaries' applications in terms of performance, communication and power requirements. Moreover based on this analysis, this deliverable will report the essential system attributes and requirements that the ExaNeSt framework should provide. Finally this deliverable will provide the porting strategy and roadmap.

New node technologies and exascale systems

This deliverable will investigate the functionality and performance of the EUROSERVER Compute Node or other high-performance Compute Nodes in the ExaNeSt infrastructrure.

Final report on the validated and optimized storage and data access infrastructure

This deliverable will provide the final report on the validated and optimized storage and data access infrastructure.

Census of the applications

This deliverable is report that descibes the HPC applications that they will be used for the evaluation of the ExaNeSt platform.

Final recommendation and future work

This deliverable will provide recommentations on the network and storage architecture based on the evaluation of the ExaNeSt platform. Moreover it will provide future plans and work that will be performed after the end of the project.

Preliminary Dissemination report

This deliverable will provide a report describing the preliminiary dissemination and communication actions.

Final Dissemination report

This deliverable will provide a report describing the final dissemination and communication actions.

Intermediate Dissemination report

This deliverable will provide a report describing the intermediate dissemination and communication actions.

Implementation notes for the storage and data access infrastructure

This deliverable will describe the implementation of the software components and tools for the HPC storage and data access infrstructure specified in D4.1.

Pubblicazioni

An Optimal Single-Path Routing Algorithm in the Datacenter Network DPillar

Autori: Alejandro Erickson, Abbas E. Kiasari, Javier Navaridas, Iain A. Stewart
Pubblicato in: IEEE Transactions on Parallel and Distributed Systems, Numero 28/3, 2017, Pagina/e 689-703, ISSN 1045-9219
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TPDS.2016.2591011

The stellar transformation: From interconnection networks to datacenter networks

Autori: Alejandro Erickson, Iain A. Stewart, Javier Navaridas, Abbas E. Kiasari
Pubblicato in: Computer Networks, Numero 113, 2017, Pagina/e 29-45, ISSN 1389-1286
Editore: Elsevier BV
DOI: 10.1016/j.comnet.2016.12.001

Efficient Sharing of Optical Resources in Low-Power Optical Networks-on-Chip

Autori: Sebastian Werner, Javier Navaridas, Mikel Luján
Pubblicato in: Journal of Optical Communications and Networking, Numero 9/5, 2017, Pagina/e 364, ISSN 1943-0620
Editore: Optical Society of America
DOI: 10.1364/jocn.9.000364

A Survey on Optical Network-on-Chip Architectures

Autori: Sebastian Werner, Javier Navaridas, Mikel Luján
Pubblicato in: ACM Computing Surveys, Numero 50/6, 2018, Pagina/e 1-37, ISSN 0360-0300
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3131346

Improved routing algorithms in the dual-port datacenter networks HCN and BCN

Autori: Alejandro Erickson, Iain A. Stewart, Jose A. Pascual, Javier Navaridas
Pubblicato in: Future Generation Computer Systems, Numero 75, 2017, Pagina/e 58-71, ISSN 0167-739X
Editore: Elsevier BV
DOI: 10.1016/j.future.2017.05.004

INRFlow: An interconnection networks research flow-level simulation framework

Autori: Javier Navaridas, Jose A. Pascual, Alejandro Erickson, Iain A. Stewart, Mikel Luján
Pubblicato in: Journal of Parallel and Distributed Computing, Numero 130, 2019, Pagina/e 140-152, ISSN 0743-7315
Editore: Academic Press
DOI: 10.1016/j.jpdc.2019.03.013

Enabling shared memory communication in networks of MPSoCs

Autori: Joshua Lant, Caroline Concatto, Andrew Attwood, Jose A. Pascual, Mike Ashworth, Javier Navaridas, Mikel Luján, John Goodacre
Pubblicato in: Concurrency and Computation: Practice and Experience, 2018, Pagina/e e4774, ISSN 1532-0626
Editore: John Wiley & Sons Inc.
DOI: 10.1002/cpe.4774

On the effects of allocation strategies for exascale computing systems with distributed storage and unified interconnects

Autori: Jose A. Pascual, Joshua Lant, Caroline Concatto, Andrew Attwood, Javier Navaridas, Mikel Luján, John Goodacre
Pubblicato in: Concurrency and Computation: Practice and Experience, 2018, Pagina/e e4784, ISSN 1532-0626
Editore: John Wiley & Sons Inc.
DOI: 10.1002/cpe.4784

On-chip wireless silicon photonics: from reconfigurable interconnects to lab-on-chip devices

Autori: Carlos García-Meca, Sergio Lechago, Antoine Brimont, Amadeu Griol, Sara Mas, Luis Sánchez, Laurent Bellieres, Nuria S Losilla, Javier Martí
Pubblicato in: Light: Science & Applications, Numero 6/9, 2017, Pagina/e e17053-e17053, ISSN 2047-7538
Editore: Nature
DOI: 10.1038/lsa.2017.53

Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development

Autori: Manolis Katevenis, Roberto Ammendola, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Piero Vicini, Giuliano Taffoni, Jose A. Pascual, Javier Navaridas, Mikel Luján, John Goodacre, Bernd Lietzow, Angelos Mouzakitis, Nikolaos Chrysos, Manolis Marazakis, Paolo Gorlani, Stefano
Pubblicato in: Microprocessors and Microsystems, Numero 61, 2018, Pagina/e 58-71, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2018.05.009

Modeling and analysis of the performance of exascale photonic networks

Autori: José Duro, Jose A. Pascual, Salvador Petit, Julio Sahuquillo, María E. Gómez
Pubblicato in: Concurrency and Computation: Practice and Experience, 2019, Pagina/e e4773, ISSN 1532-0626
Editore: John Wiley & Sons Inc.
DOI: 10.1002/cpe.4773

Iris

Autori: Anastasios Papagiannis, Giorgos Saloustros, Manolis Marazakis, Angelos Bilas
Pubblicato in: ACM SIGOPS Operating Systems Review, Numero 50/1, 2017, Pagina/e 3-11, ISSN 0163-5980
Editore: ACM
DOI: 10.1145/3041710.3041713

Receive-Side Notification for Enhanced RDMA in FPGA Based Networks

Autori: Joshua Lant, Andrew Attwood, Javier Navaridas, Mikel Lujan, John Goodacre
Pubblicato in: Architecture of Computing Systems – ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings, Numero 11479, 2019, Pagina/e 224-235, ISBN 978-3-030-18655-5
Editore: Springer International Publishing
DOI: 10.1007/978-3-030-18656-2_17

On the Effects of Data-Aware Allocation on Fully Distributed Storage Systems for Exascale

Autori: Jose A. Pascual, Caroline Concatto, Joshua Lant, Javier Navaridas
Pubblicato in: Euro-Par 2017: Parallel Processing Workshops - Euro-Par 2017 International Workshops, Santiago de Compostela, Spain, August 28-29, 2017, Revised Selected Papers, Numero 10659, 2018, Pagina/e 725-736, ISBN 978-3-319-75177-1
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-75178-8_58

A CAM-Free Exascalable HPC Router for Low-Energy Communications

Autori: Caroline Concatto, Jose A. Pascual, Javier Navaridas, Joshua Lant, Andrew Attwood, Mikel Lujan, John Goodacre
Pubblicato in: Architecture of Computing Systems – ARCS 2018, Numero 10793, 2018, Pagina/e 99-111, ISBN 978-3-319-77609-5
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-77610-1_8

Direct N-body Code on Low-Power Embedded ARM GPUs

Autori: David Goz, Sara Bertocco, Luca Tornatore, Giuliano Taffoni
Pubblicato in: Intelligent Computing - Proceedings of the 2019 Computing Conference, Volume 1, Numero 997, 2019, Pagina/e 179-193, ISBN 978-3-030-22870-5
Editore: Springer International Publishing
DOI: 10.1007/978-3-030-22871-2_14

The brain on low power architectures: Efficient simulation of cortical slow waves and asynchronous states

Autori: R. Ammendola, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, L. Pontisso, F. Simula, P. Vicini
Pubblicato in: Advances in Parallel Computing, Numero Vol. 32, 2018, Pagina/e 760-769
Editore: IOS Press
DOI: 10.3233/978-1-61499-843-3-760

Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links

Autori: Sebastian Werner, Javier Navaridas, Mikel Lujan
Pubblicato in: 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, Pagina/e 265-276, ISBN 978-1-5090-4985-1
Editore: IEEE
DOI: 10.1109/hpca.2017.23

Network-on-chip evaluation for a novel neural architecture

Autori: Markos Kynigos, Javier Navaridas, Luis A. Plana, Steve Furber
Pubblicato in: Proceedings of the 15th ACM International Conference on Computing Frontiers - CF '18, 2018, Pagina/e 216-219, ISBN 9781-450357616
Editore: ACM Press
DOI: 10.1145/3203217.3203268

Subchannel Scheduling for Shared Optical On-chip Buses

Autori: Sebastian Werner, Javier Navaridas, Mikel Lujan
Pubblicato in: 2017 IEEE 25th Annual Symposium on High-Performance Interconnects (HOTI), 2017, Pagina/e 49-56, ISBN 978-1-5386-1013-8
Editore: IEEE
DOI: 10.1109/hoti.2017.18

High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings

Autori: Jose A. Pascual, Javier Navaridas
Pubblicato in: Proceedings of the 2018 International Conference on Supercomputing - ICS '18, 2018, Pagina/e 129-138, ISBN 9781-450357838
Editore: ACM Press
DOI: 10.1145/3205289.3205307

Design Exploration of Multi-tier interconnection networks s for Exascale systems

Autori: Navaridas, J., Lant, J., Pascual Saiz, J., Luján, M., & Goodacre, A.
Pubblicato in: ICPP 2019 : International Conference on Parallel Processing, 2019, Pagina/e TBD
Editore: ACM

Scalability of a Silicon Photonic Switch for High Performance Interconnects

Autori: M. Kynigos, J. Navaridas and J.A. Pascual
Pubblicato in: Emit, 2019
Editore: Emit

Direct Communications between Disributed FPGA

Autori: J. Lant, J. Navaridas
Pubblicato in: Emit, 2019
Editore: Emit

Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems

Autori: Francesco Simula, Elena Pastorelli, Pier Stanislao Paolucci, Michele Martinelli, Alessandro Lonardo, Andrea Biagioni, Cristiano Capone, Fabrizio Capuani, Paolo Cretaro, Giulia De Bonis, Francesca Lo Cicero, Luca Pontisso, Piero Vicini, Roberto Ammendola
Pubblicato in: 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2019, Pagina/e 283-290, ISBN 978-1-7281-1644-0
Editore: IEEE
DOI: 10.1109/empdp.2019.8671627

Accurate Congestion Control for RDMA Transfers

Autori: Dimitris Giannopoulos, Nikos Chrysos, Evangelos Mageiropoulos, Giannis Vardas, Leandros Tzanakis, Manolis Katevenis
Pubblicato in: 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018, Pagina/e 1-8, ISBN 978-1-5386-4893-3
Editore: IEEE
DOI: 10.1109/nocs.2018.8512155

Gaussian and Exponential Lateral Connectivity on Distributed Spiking Neural Network Simulation

Autori: Elena Pastorelli, Pier Stanislao Paolucci, Francesco Simula, Andrea Biagioni, Fabrizio Capuani, Paolo Cretaro, Giulia De Bonis, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Luca Pontisso, Piero Vicini, Roberto Ammendola
Pubblicato in: 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), 2018, Pagina/e 658-665, ISBN 978-1-5386-4975-6
Editore: IEEE
DOI: 10.1109/pdp2018.2018.00110

An Efficient Memory-Mapped Key-Value Store for Flash Storage

Autori: Anastasios Papagiannis, Giorgos Saloustros, Pilar González-Férez, Angelos Bilas
Pubblicato in: Proceedings of the ACM Symposium on Cloud Computing - SoCC '18, 2018, Pagina/e 490-502, ISBN 9781-450360111
Editore: ACM Press
DOI: 10.1145/3267809.3267824

Workload Characterization for Exascale Computing Networks

Autori: Jose Duro, Salvador Petit, Julio Sahuquillo, Maria Gomez
Pubblicato in: 2018 International Conference on High Performance Computing & Simulation (HPCS), 2018, Pagina/e 383-389, ISBN 978-1-5386-7879-4
Editore: IEEE
DOI: 10.1109/hpcs.2018.00069

The next Generation of Exascale-class Systems: the ExaNeSt Project

Autori: R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero, A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Simula, P. Vicini, G. Taffoni, John Goodacree, Mikel Lujn, J. Navaridas, J. P. Saiz, N. Chrysos, and M. Katevenis for the ExaNeSt team
Pubblicato in: Euromicro Conference on Digital System Design (DSD 2017), 2017
Editore: IEEE
DOI: 10.5281/zenodo.823595

The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems

Autori: M. Katevenis, N. Chrysos, M. Marazakis, I. Mavroidis, F. Chaix, N. Kallimanis, J. Navaridas, J. Goodacre, P. Vicini, A. Biagioni, P. S. Paolucci, A. Lonardo, E. Pastorelli, F. Lo Cicero, R. Ammendola, P. Hopton, P. Coates, G. Taffoni, S. Cozzini, M. Kersten, Y. Zhang, J. Sahuquillo, S. Lechago, C. Pinto, B. Lietzow, D. Everett, G. Perna
Pubblicato in: 2016 Euromicro Conference on Digital System Design (DSD), 2016, Pagina/e 60-67, ISBN 978-1-5090-2817-7
Editore: IEEE
DOI: 10.1109/DSD.2016.106

Modeling a Photonic Network for Exascale Computing

Autori: Jose Duro, Salvador Petit, Julio Sahuquillo and Maria E. Gomez
Pubblicato in: 3rd International Workshop on Modeling and Simulation of Parallel and Distributed Systems (MSPDS 2017), 2017
Editore: IEEE
DOI: 10.5281/zenodo.823624

Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework

Autori: Jose Puche, Sergio Lechago, Salvador Petit, María E. Gómez and Julio Sahuquillo
Pubblicato in: Workshop on Modeling and Simulation of Parallel and Distributed Systems, 2016
Editore: IEEE
DOI: 10.5281/zenodo.804004

Designing an exascale interconnect using multi-objective optimization

Autori: Jose A. Pascual, Joshua Lant, Andrew Attwood, Caroline Concatto, Javier Navaridas, Mikel Lujan, John Goodacre
Pubblicato in: 2017 IEEE Congress on Evolutionary Computation (CEC), 2017, Pagina/e 2209-2216, ISBN 978-1-5090-4601-0
Editore: IEEE
DOI: 10.1109/CEC.2017.7969572

User-space I/O for μs-level storage devices

Autori: Anastasios Papagiannis, Giorgos Saloustros, Manolis Marazakis, Angelos Bilas
Pubblicato in: Michela Taufer, Bernd Mohr, Julian M. Kunkel (Eds.): High Performance Computing, LNCS 9945, ISC High Performance 2016 International Workshops ExaComm, E-MuCoCoS, HPC-IODC, IXPUG, IWOPH, P3MA, VHPC, WOPSSS, Numero LNCS 9945, 2016, Pagina/e 638-648, ISBN 978-3-319-46078-9
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-46079-6_44

Lightweight and Generic RDMA Engine Para-virtualization for the KVM Hypervisor

Autori: Angelos Mouzakitis, Christian Pinto, Nikolay Nikolaev, Alvise Rigo, Daniel Raho, Babis Aronis, Manolis Marazakis
Pubblicato in: 2017 International Conference on High Performance Computing & Simulation (HPCS 2017), 2017
Editore: IEEE
DOI: 10.5281/zenodo.807607

Virtualized Multi-Channel RDMAwith Software-Defined Scheduling

Autori: Kyriakos Paraskevas, Nikolaos Chrysos, Vassilis Papaefstathiou, Pantelis Xirouchakis, Panagiotis Peristerakis, Michalis Giannioudis, Manolis Katevenis
Pubblicato in: Procedia Computer Science, Numero 136, 2018, Pagina/e 82-90, ISSN 1877-0509
Editore: Science Direct
DOI: 10.1016/j.procs.2018.08.240

High signal-to-noise ratio ultra-compact lab-on-a-chip microflow cytometer enabled by silicon optical antennas

Autori: Sergio Lechago, Carlos García-Meca, Nuria Sánchez-Losilla, Amadeu Griol, Javier Martí
Pubblicato in: Optics Express, Numero 26/20, 2018, Pagina/e 25645, ISSN 1094-4087
Editore: Optical Society of America
DOI: 10.1364/oe.26.025645

Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project

Autori: R Ammendola, A Biagioni, P Cretaro, O Frezza, F Lo Cicero, A Lonardo, M Martinelli, P S Paolucci, E Pastorelli, F Pisani, F Simula, P Vicini, J Navaridas, F Chaix, N Chrysos, M Katevenis, V Papaeustathiou
Pubblicato in: Journal of Physics: Conference Series, Numero 898, 2017, Pagina/e 082045, ISSN 1742-6588
Editore: Institute of Physics
DOI: 10.1088/1742-6596/898/8/082045

Large scale low power computing system: status of network design in ExaNeSt and EuroEXA projects

Autori: R. Ammendola, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, L. Pontissio, F. Simula and P. Vicini
Pubblicato in: Advances in Parallel Computing, 2018
Editore: IEEE
DOI: 10.3233/978-1-61499-843-3-750

Enabling Standalone FPGA Computing

Autori: J. Lant, J. Navaridas, A. Attwood, M. Lujan and J. Goodacre
Pubblicato in: IEEE Symposium on High Performance Interconnects, 2019
Editore: IEEE

Direct N-body code designed for cluster based on heterogeneous computational nodes

Autori: D. Goz, L. Tornatore, S. Bertocco & G. Taffoni
Pubblicato in: INAF-OATS Technical Report, 2018
Editore: INAF
DOI: 10.20371/inaf/pub/2018_00005

Direct N-Body code designed for heterogeneous platforms

Autori: D. Goz, S. Bertocco, L. Tornatore, G. Taffoni
Pubblicato in: INAF, 2018
Editore: INAF
DOI: 10.20371/inaf/pub/2018_00002

Software and Hardware co-design for low power HPC Platforms

Autori: M. Ploumidis, N.D. Kallimanis, M. Asiminakis, N. Chryos, P. Xirouchakis, M. Gianoudis, L. Tzanakis, N. Dimou, A. Psistakis, P. Peristerkis, G. Kalokairinos, V. Papaefstathiou and M. Katevenis
Pubblicato in: Exacomm, 2019
Editore: Exacomm

Enabling Standalone FPGA Computing

Autori: Joshua Lant, Javier Navaridas, Andrew Attwood, Mikel Lujan and John Goodacre
Pubblicato in: IEEE Micro, 2019
Editore: IEEE

Performance of direct N-body code on ARM64 SoC

Autori: D. Goz, L. Tornatore, S. Bertocco & G. Taffoni
Pubblicato in: INAF-OATS Technical Report, 2018
Editore: INAF
DOI: 10.20371/inaf/pub/2018_00006

Distributed Processing and Transaction Replication in MonetDB - Towards a Scalable Analytical Database System in the Cloud

Autori: Ying Zhang, Dimitar Nedev, Panagiotis Koutsourakis, and Martin Kersten
Pubblicato in: Final Public Workshop from LeanBigData and CoherentPaaS, 2016
Editore: n/a
DOI: 10.5281/zenodo.803988

Diritti di proprietà intellettuale

Pumped Primary Coolant

Numero candidatura/pubblicazione: 1 619987.9
Data: 2016-11-25
Candidato/i: ICEOTOPE RESEARCH & DEVELOPMENT LTD

Expanding Thermal Bus

Numero candidatura/pubblicazione: GB 1613234.2
Data: 2016-09-14
Candidato/i: ICEOTOPE RESEARCH & DEVELOPMENT LTD

Closed Loop Mains Water Control

Numero candidatura/pubblicazione: GB 1621085.8
Data: 2017-11-27
Candidato/i: ICEOTOPE RESEARCH & DEVELOPMENT LTD

Dynamic Max-Min Fair Rate Regulation Apparatuses, Methods, and Systems

Numero candidatura/pubblicazione: US 2016/0087899 A1
Data: 2015-09-24

Power Supply Bath

Numero candidatura/pubblicazione: GB 1714313.2
Data: 2017-09-06
Candidato/i: ICEOTOPE RESEARCH & DEVELOPMENT LTD

AN IMMERSION COOLING SYSTEM

Numero candidatura/pubblicazione: EP 16777786
Data: 2016-10-03
Candidato/i: ICEOTOPE RESEARCH & DEVELOPMENT LTD

Dynamic Max-Min Fair Rate Regulation Apparatuses, Methods, and Systems

Numero candidatura/pubblicazione: US 2016/0087899 A1
Data: 2015-09-24

I/O Board

Numero candidatura/pubblicazione: 1 619976.2
Data: 2016-11-25
Candidato/i: ICEOTOPE RESEARCH & DEVELOPMENT LTD

Pumped Primary Coolant

Numero candidatura/pubblicazione: 1 619987.9
Data: 2016-11-25
Candidato/i: ICEOTOPE RESEARCH & DEVELOPMENT LTD

Coolant Delivery Nozzle

Numero candidatura/pubblicazione: GB 1714308.2
Data: 2017-09-06
Candidato/i: ICEOTOPE RESEARCH & DEVELOPMENT LTD

I/O Board

Numero candidatura/pubblicazione: 1 619976.2
Data: 2016-11-25
Candidato/i: ICEOTOPE RESEARCH & DEVELOPMENT LTD

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Pubblicazioni

Diritti di proprietà intellettuale

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