Periodic Reporting for period 1 - IT2 (IC Technology for the 2nm Node)
Reporting period: 2020-06-01 to 2021-08-31
In the coming decade, demands from new applications like mobile applications, high-performance computing, artificial intelligence and machine learning and so on, will drive the need to push technology as far as possible. In addition, the current geopolitical context, the semiconductor chip shortage and the complexity of the semiconductor value chain, have brought extra attention to this sector. Members of the IT2 consortium are world leading equipment, tool and metrology suppliers ambitiously pursuing the extension of the scaled semiconductor technology roadmaps and thereby maintain competence in advanced More Moore technology in Europe to support leading edge manufacturing. The overall goal of the IT2 project is to develop key technologies to bring the Semiconductor roadmap to the 2nm node. To achieve this goal, three main axes are covered, advanced lithography (WP2), advanced metrology (WP3) as well as process and module development (WP4). The specific objectives are:
- Lithography: 2nm node Multi-Patterning EUV scanner, active thermal management for EUV mirrors and a novel high power EUV source. 30% productivity increase and/or to mitigate stochastic (random) errors compared to SoA while reducing the OPO x2.
- Process & Module Exploration: keep pace with Moore’s scaling law and meet the performance, power, area and cost (PPAC) specifications for the 2nm node. Develop new device architectures: gate all around nanosheet (GAA NS) and CFET devices. Develop new device scaling boosters: fork sheet (FS) and Super Via (SV). Explore options beyond the area scaling with Circuit Scaling and Architecture Scaling: Design Technology Co-Optimization (DTCO), 3D System Technology Co-Optimization (STCO).
- Metrology: Develop metrology capabilities (HW, SW) to address 2nm tech node with improved sensitivity, accuracy and precision while maintaining productivity and overall efficiency, for statistical process control in HVM. Address metrology needs associated to STCO driven Circuit and Architecture scaling solutions, such as “Sequential 3D” and “Wafer Back-side Power Distribution Network”, wafer-to-wafer bonding, wafer thinning, and TSV processing steps.
- Lithography: 2nm node Multi-Patterning EUV scanner, active thermal management for EUV mirrors and a novel high power EUV source. 30% productivity increase and/or to mitigate stochastic (random) errors compared to SoA while reducing the OPO x2.
- Process & Module Exploration: keep pace with Moore’s scaling law and meet the performance, power, area and cost (PPAC) specifications for the 2nm node. Develop new device architectures: gate all around nanosheet (GAA NS) and CFET devices. Develop new device scaling boosters: fork sheet (FS) and Super Via (SV). Explore options beyond the area scaling with Circuit Scaling and Architecture Scaling: Design Technology Co-Optimization (DTCO), 3D System Technology Co-Optimization (STCO).
- Metrology: Develop metrology capabilities (HW, SW) to address 2nm tech node with improved sensitivity, accuracy and precision while maintaining productivity and overall efficiency, for statistical process control in HVM. Address metrology needs associated to STCO driven Circuit and Architecture scaling solutions, such as “Sequential 3D” and “Wafer Back-side Power Distribution Network”, wafer-to-wafer bonding, wafer thinning, and TSV processing steps.
During the first period of the project, the focus was on:
WP2 (lithography): the requirements release, setting up the infrastructure and equipment needed to develop the new modules for the 0.33 NA EUV tool for 2nm node patterning, initiating the first designs, tests and prototypes in line with ASML’s input and samples. The first activities concept designs and architecture have also started for active thermal management and improved source as part of the EUV scanner, including innovative litho-optics for 2nm node multi-patterning, increased EUV power source and thermal management, wafer stage developments, alignment techniques, contamination control, and innovative High Power EUV source.
Wp3 (Metrology): activities on metrology and analytical systems for characterization and control of 2nm node process steps, process modules and device architectures have commenced; addressing the System Technology Co-Optimization (STCO) specific metrology needs (through silicon metrology, alignment control and hybrid wafer bonding process control); and demonstrating the metrology capabilities developed on imec relevant test wafers and comparison of results obtained with the different and complementary metrology techniques.
WP4( Process and module exploration): process and module development, the partners delivered the first results on patterning options, BEOL, ultimate CMOS scaling, and system Technology Co-Optimization (STCO) for 2nm node have been demonstrated. : (1) the qualification of EUV Self-Aligned Litho-Etch-Litho-Etch for 21nm and 18nm pitch, and (2) the demonstration of 18nm pitch L/S gratings using Single Exposure hNA EUV interference lithography (Figure 1). Related to BEOL: (1) the module build completion and first electrical results for: 18nm pitch semi-damascene integration, and Mx - Via - Mx+3 Super Via scaling booster integration (Figure 2), (2) monitoring cleanroom volatile organic contamination using Proton Transfer Reaction Mass Spectrometry and (3) material development for Thin Film Transistor power switches. Regarding Ultimate CMOS scaling: (1) first electrical data for integrated CFET device at relaxed pitch and (2) demonstration of Replacement Metal Gate module integration for Forksheet CMOS integration (Figure 3). Related to System Technology Co-optimization: (1) Power Performance and Area performance evaluation for Buried Power Rail, (2) substrates, processes and hard ware development for bonding dielectrics, accurate W2W bonding, handling stacked substrates, active layer transfer donor wafers, UV laser technology for low thermal budget dopant anneal, yielding a successful (morphological) proof of concept demonstration for 3D sequential integration - RF on Logic application - (Figure 4) and Back Side Power Delivery Network (BS PDN) and, (3) material development for Ovonic Threshold Switching and Phase Change memory devices.
WP2 (lithography): the requirements release, setting up the infrastructure and equipment needed to develop the new modules for the 0.33 NA EUV tool for 2nm node patterning, initiating the first designs, tests and prototypes in line with ASML’s input and samples. The first activities concept designs and architecture have also started for active thermal management and improved source as part of the EUV scanner, including innovative litho-optics for 2nm node multi-patterning, increased EUV power source and thermal management, wafer stage developments, alignment techniques, contamination control, and innovative High Power EUV source.
Wp3 (Metrology): activities on metrology and analytical systems for characterization and control of 2nm node process steps, process modules and device architectures have commenced; addressing the System Technology Co-Optimization (STCO) specific metrology needs (through silicon metrology, alignment control and hybrid wafer bonding process control); and demonstrating the metrology capabilities developed on imec relevant test wafers and comparison of results obtained with the different and complementary metrology techniques.
WP4( Process and module exploration): process and module development, the partners delivered the first results on patterning options, BEOL, ultimate CMOS scaling, and system Technology Co-Optimization (STCO) for 2nm node have been demonstrated. : (1) the qualification of EUV Self-Aligned Litho-Etch-Litho-Etch for 21nm and 18nm pitch, and (2) the demonstration of 18nm pitch L/S gratings using Single Exposure hNA EUV interference lithography (Figure 1). Related to BEOL: (1) the module build completion and first electrical results for: 18nm pitch semi-damascene integration, and Mx - Via - Mx+3 Super Via scaling booster integration (Figure 2), (2) monitoring cleanroom volatile organic contamination using Proton Transfer Reaction Mass Spectrometry and (3) material development for Thin Film Transistor power switches. Regarding Ultimate CMOS scaling: (1) first electrical data for integrated CFET device at relaxed pitch and (2) demonstration of Replacement Metal Gate module integration for Forksheet CMOS integration (Figure 3). Related to System Technology Co-optimization: (1) Power Performance and Area performance evaluation for Buried Power Rail, (2) substrates, processes and hard ware development for bonding dielectrics, accurate W2W bonding, handling stacked substrates, active layer transfer donor wafers, UV laser technology for low thermal budget dopant anneal, yielding a successful (morphological) proof of concept demonstration for 3D sequential integration - RF on Logic application - (Figure 4) and Back Side Power Delivery Network (BS PDN) and, (3) material development for Ovonic Threshold Switching and Phase Change memory devices.
The innovations planned in IT2 are centred around creation of Lithography equipment, Process, Metrology and Wafer handling tools, all of them necessary for to demonstrate technology breakthroughs to bring the Semiconductor roadmap to the 2nm node.
The first period of the project has generated many State of the Art results, leading to dissemination activities, including 6 Peer reviewed publications, 33 participation to conferences, 29 prototypes, including new products, new processes and methods, 11 of these innovations are new to the market.
Some the results include: demonstration of SE hNA EUV for 18nm pitch, semi-damascene integration at 18nm metal pitch and Super Via scaling integration for Mx-SV-Mx+3 Via’s, CFET device integration at relaxed pitch, Forksheet device module development, key process and module development for 3D sequential integration and Back Side Power Delivery Network.
The first period of the project has generated many State of the Art results, leading to dissemination activities, including 6 Peer reviewed publications, 33 participation to conferences, 29 prototypes, including new products, new processes and methods, 11 of these innovations are new to the market.
Some the results include: demonstration of SE hNA EUV for 18nm pitch, semi-damascene integration at 18nm metal pitch and Super Via scaling integration for Mx-SV-Mx+3 Via’s, CFET device integration at relaxed pitch, Forksheet device module development, key process and module development for 3D sequential integration and Back Side Power Delivery Network.