Periodic Reporting for period 3 - IT2 (IC Technology for the 2nm Node)
Reporting period: 2022-09-01 to 2023-09-30
The overall goal of the IT2 project is to develop key technologies to bring the Semiconductor roadmap to the 2nm node. To achieve this goal, three main axes are covered, advanced lithography (WP2), advanced metrology (WP3) as well as process and module development (WP4).
The specific objectives are:
- Lithography: 2nm node Multi-Patterning EUV scanner, active thermal management for EUV mirrors and a novel high power EUV source. 30% productivity increase and/or to mitigate stochastic (random) errors compared to SoA (State of the Art) while reducing the OPO x2.
- Metrology: Develop metrology capabilities (Hardware, Software) to address 2nm tech node with improved sensitivity, accuracy and precision while maintaining productivity and overall efficiency, for statistical process control in HVM (High Volume Manufacturing). Address metrology needs associated to STCO (System Technology Co-Optimization) driven Circuit and Architecture scaling solutions, such as “Sequential 3D” and “Wafer Back-side Power Distribution Network”, wafer-to-wafer bonding, wafer thinning, and TSV processing steps.
- Process & Module Exploration: keep pace with Moore’s scaling law and meet the performance, power, area and cost (PPAC) specifications for the 2nm node. Assess, benchmark device architecture options: gate all around nanosheet (GAA NS), Forksheet (FS) and CFET device. Develop new scaling boosters like fully self-aligned Via (FSAV) and super via (SV). Explore options beyond 2D area scaling such as backside power delivery network (BS PDN), 3D sequential integration.
The specific objectives are:
- Lithography: 2nm node Multi-Patterning EUV scanner, active thermal management for EUV mirrors and a novel high power EUV source. 30% productivity increase and/or to mitigate stochastic (random) errors compared to SoA (State of the Art) while reducing the OPO x2.
- Metrology: Develop metrology capabilities (Hardware, Software) to address 2nm tech node with improved sensitivity, accuracy and precision while maintaining productivity and overall efficiency, for statistical process control in HVM (High Volume Manufacturing). Address metrology needs associated to STCO (System Technology Co-Optimization) driven Circuit and Architecture scaling solutions, such as “Sequential 3D” and “Wafer Back-side Power Distribution Network”, wafer-to-wafer bonding, wafer thinning, and TSV processing steps.
- Process & Module Exploration: keep pace with Moore’s scaling law and meet the performance, power, area and cost (PPAC) specifications for the 2nm node. Assess, benchmark device architecture options: gate all around nanosheet (GAA NS), Forksheet (FS) and CFET device. Develop new scaling boosters like fully self-aligned Via (FSAV) and super via (SV). Explore options beyond 2D area scaling such as backside power delivery network (BS PDN), 3D sequential integration.
Work package 2 Lithography
For the modular key breakthrough EUV platform technologies, including innovative litho-optics for 2nm node multi-patterning, increased EUV power source and thermal management, wafer stage developments, alignment techniques, contamination control, and innovative High Power EUV source, significant progress has been made on all areas, see Figure 1 for some of these results. All innovations have been demonstrated. For Active Thermal Management for EUV Projection Lens Mirrors, ZEISS has integrated the first POB and shipped it to ASML. Last but not least, all modules, i.e. module SOURCE containing the EUV power source; module TOP for the mask logistics; module MID containing the optics and module BOTTOM for the wafer logistics have been integrated at different locations over the globe and afterwards shipped to ASML Veldhoven where they have been integrated into the first EUV lithography machine for the 2nm node multi-patterning (NXE:3800), see Figure 2. In October 2023, the first image in the (wafer) resist has been successfully achieved.
Work package 3 Metrology
Activities on metrology and analytical systems for characterization and control of 2nm node process steps, process modules and device architectures have continued for the four areas of In-line Overlay Metrology, In-line Optical Metrology, X-ray, Ion and Electron based Metrology and Metrology evaluation and benchmarking on IMEC relevant test wafers. All WP3 participants have finished their IT2 R&D activities with all milestones and deliverables being completed. Experimental results have been reported in individual partner deliverable reports as well as a joint report on analyzing 2nm node representative IMEC forksheet and SiGe samples.
KLA and Unity have developed improved techniques and tools for optical overlay, including for wafer bonding. Nova has developed a novel optical material metrology technique, while Semilab developed new Ellipsometry techniques and a new system. AMIL has developed an application for visualization and fast modelling of Edge Placement Error as well as CD, overlay and other metrology parameters, based on massive ebeam metrology measurements. TNO and UPB have collaborated on the exploration of the spatial resolution limits of the innovative IR-AFM technique and its applicability on the 2nm technology structures, including also the development of an FIB based μm-sample preparation method for this. UPB has also extended the capability of their μRaman equipment, enabling strain analysis on very shallow layers. Bruker has developed technology leading to new XRF and XRD systems, along with collaborating with PTB on GIXRF techniques and results interpretation for patterned samples. Thermo Fisher has performed R&D on new prototype TEM technology for the chemical and physical analysis of 2nm node devices. Cameca has developed hardware and software modules for integration in a new SIMS system. Figure 3 shows some of the work package 3 results.
Work package 4 Process and module exploration
Key achievements related to patterning include: selection of metal organic resists for 24nm Lines/Spaces use-case hNA EUV single patterning (Figure 4), for holes and pillars single-patterning, successful resolution of 32nm Center-to-Center pitches, and the development of machine learning algorithm for edge placement error contributors break down. Related to BEOL: sheet resistance reduction of thin metals using UV laser anneal, and related to clean room contamination, algorithm development for unknown compound identification. Regarding ultimate CMOS scaling: module development for bottom dielectric isolation (BDI) integration for forksheet device (Figure 5), p-type contacts ~2E-9 cm2 with Ga plasma immersion ion implantation, morphological proof of concept of CFET device at relaxed pitch (Figure 6), and Smart CutTM technology for monolithic CFET with embedded middle dielectric isolation, MDI (Figure 7). Related to System Technology Co-optimization: chip level power integrity benefit demonstration for Backside Power Delivery Network (Figure 8), Modular Bond Alignment module for 3D wafer stacking (Figure 9), electrically functional 3D sequential integrated devices (Figure 10), versatile wafer sorter for handling 3D stacked substrates (Figure 11), and (Figure 12) electrical functional FinFET device wafer with backside metal for BS PDN functionality.
For the modular key breakthrough EUV platform technologies, including innovative litho-optics for 2nm node multi-patterning, increased EUV power source and thermal management, wafer stage developments, alignment techniques, contamination control, and innovative High Power EUV source, significant progress has been made on all areas, see Figure 1 for some of these results. All innovations have been demonstrated. For Active Thermal Management for EUV Projection Lens Mirrors, ZEISS has integrated the first POB and shipped it to ASML. Last but not least, all modules, i.e. module SOURCE containing the EUV power source; module TOP for the mask logistics; module MID containing the optics and module BOTTOM for the wafer logistics have been integrated at different locations over the globe and afterwards shipped to ASML Veldhoven where they have been integrated into the first EUV lithography machine for the 2nm node multi-patterning (NXE:3800), see Figure 2. In October 2023, the first image in the (wafer) resist has been successfully achieved.
Work package 3 Metrology
Activities on metrology and analytical systems for characterization and control of 2nm node process steps, process modules and device architectures have continued for the four areas of In-line Overlay Metrology, In-line Optical Metrology, X-ray, Ion and Electron based Metrology and Metrology evaluation and benchmarking on IMEC relevant test wafers. All WP3 participants have finished their IT2 R&D activities with all milestones and deliverables being completed. Experimental results have been reported in individual partner deliverable reports as well as a joint report on analyzing 2nm node representative IMEC forksheet and SiGe samples.
KLA and Unity have developed improved techniques and tools for optical overlay, including for wafer bonding. Nova has developed a novel optical material metrology technique, while Semilab developed new Ellipsometry techniques and a new system. AMIL has developed an application for visualization and fast modelling of Edge Placement Error as well as CD, overlay and other metrology parameters, based on massive ebeam metrology measurements. TNO and UPB have collaborated on the exploration of the spatial resolution limits of the innovative IR-AFM technique and its applicability on the 2nm technology structures, including also the development of an FIB based μm-sample preparation method for this. UPB has also extended the capability of their μRaman equipment, enabling strain analysis on very shallow layers. Bruker has developed technology leading to new XRF and XRD systems, along with collaborating with PTB on GIXRF techniques and results interpretation for patterned samples. Thermo Fisher has performed R&D on new prototype TEM technology for the chemical and physical analysis of 2nm node devices. Cameca has developed hardware and software modules for integration in a new SIMS system. Figure 3 shows some of the work package 3 results.
Work package 4 Process and module exploration
Key achievements related to patterning include: selection of metal organic resists for 24nm Lines/Spaces use-case hNA EUV single patterning (Figure 4), for holes and pillars single-patterning, successful resolution of 32nm Center-to-Center pitches, and the development of machine learning algorithm for edge placement error contributors break down. Related to BEOL: sheet resistance reduction of thin metals using UV laser anneal, and related to clean room contamination, algorithm development for unknown compound identification. Regarding ultimate CMOS scaling: module development for bottom dielectric isolation (BDI) integration for forksheet device (Figure 5), p-type contacts ~2E-9 cm2 with Ga plasma immersion ion implantation, morphological proof of concept of CFET device at relaxed pitch (Figure 6), and Smart CutTM technology for monolithic CFET with embedded middle dielectric isolation, MDI (Figure 7). Related to System Technology Co-optimization: chip level power integrity benefit demonstration for Backside Power Delivery Network (Figure 8), Modular Bond Alignment module for 3D wafer stacking (Figure 9), electrically functional 3D sequential integrated devices (Figure 10), versatile wafer sorter for handling 3D stacked substrates (Figure 11), and (Figure 12) electrical functional FinFET device wafer with backside metal for BS PDN functionality.
All developments in this project are geared to move the capability of the semiconductor industry beyond the present state of the art.
The innovations planned in IT2 are centered around creation of Lithography equipment, Process, Metrology and Wafer handling tools, all of them necessary to demonstrate technology breakthroughs to bring the Semiconductor roadmap to the 2nm node.
Some of the results include: a 0.33 NA EUV lithography machine for the 2nm node, resist selection for hNA EUV, fully self-aligned via for semi-damascene integration, dielectric wall and bottom dielectric modules for forksheet devices, hardware for accurate alignment in 3D substrate stacking, demonstration of 3D sequential integration, demonstration of backside power delivery network.
The innovations planned in IT2 are centered around creation of Lithography equipment, Process, Metrology and Wafer handling tools, all of them necessary to demonstrate technology breakthroughs to bring the Semiconductor roadmap to the 2nm node.
Some of the results include: a 0.33 NA EUV lithography machine for the 2nm node, resist selection for hNA EUV, fully self-aligned via for semi-damascene integration, dielectric wall and bottom dielectric modules for forksheet devices, hardware for accurate alignment in 3D substrate stacking, demonstration of 3D sequential integration, demonstration of backside power delivery network.