Periodic Reporting for period 1 - MEMRINESS (Memristive Neurons and Synapses for Neuromorphic Edge Computing)
Período documentado: 2022-05-01 hasta 2024-10-31
An unsustainable technological revolution
The cloud-based approach to data classification, where computation is performed remotely in massive data centres, has recently been challenged by the edge computing paradigm. This paradigm has enabled real-time data processing at the edge of the network, ideally next to the sensor collecting the data, and has led to our smart systems becoming more and more connected. These systems need to process ever-increasing amounts of data, while at the same time being low-power, area-efficient and able to interact with the outside world in real time. There is therefore a need to explore unconventional hardware solutions that can meet these stringent requirements.
Brain-inspired architectures, in particular Spiking Neural Networks (SNNs), are promising candidates for achieving low-latency computation and stateful, energy-efficient operations. However, their current implementations are primarily based on digital or mixed-signal complementary metal-oxide-semiconductor (CMOS) technologies, which pose challenges in meeting the demanding memory, area and power constraints of edge computing. In addition, the implementation of multi-timescale dynamics in CMOS technology is extremely challenging and comes at the cost of a non-negligible increase in circuit complexity and area. Indeed, multi-timescale dynamics is shown by advanced learning theories to be essential in cognitive systems because it enables the system to react quickly, e.g. to avoid an object on a collision course or to detect an epileptic seizure, and to adapt to slow changes, e.g. ageing or wear of mechanical parts.
In this context, emerging memory technology, with its unique characteristics and capabilities, holds great promise for the design of such cognitive systems. Emerging memory devices are nanoscale devices that can change their conductivity when exposed to appropriate electrical stimuli. They offer fast and energy-efficient tunable volatile and non-volatile memory and are therefore well suited for storing SNN parameters. Exploiting their unique properties, such as operating voltages compatible with current CMOS technology and analogue neural/synaptic-like behaviour, offers an attractive opportunity to realise energy-efficient and massively parallel computing architectures. Indeed, if properly combined with CMOS technology, these features can extend the functionality of current artificial intelligence (AI) systems, enabling efficient computation, neural dynamics and synaptic plasticity, which are essential features for emulating the functionality of the brain in hardware. However, achieving this goal is still an open challenge at several levels, from device fabrication to integration with circuitry and architecture.
Objectives of MEMRINESS
The aim of the MEMRINESS project is to create new fundamental computing primitives that will overcome the current challenges for the deployment of intelligent systems at the edge. At the core of MEMRINESS is the development of neurons and synapses that exploit the intrinsic physical properties and dynamics of emerging volatile and non-volatile memory devices to enable the design of compact, power-efficient SNNs with multi-timescale dynamics.
The design of high-performance hardware AI systems relies on the synergistic development of emerging memory devices, circuits and learning algorithms. This approach requires system-technology co-optimisation (STCO) of emerging memory devices and CMOS circuits to enable seamless integration and exploit the strengths of both technologies. Indeed, the co-design of devices, circuits and algorithms requires the identification and resolution of issues related to device variability, scalability and system integration. Through the synergistic co-development of memristive devices, CMOS circuits and innovative algorithms, MEMRINESS will pave the way for intelligent edge systems capable of performing complex cognitive tasks.
The cloud-based approach to data classification, where computation is performed remotely in massive data centres, has recently been challenged by the edge computing paradigm. This paradigm has enabled real-time data processing at the edge of the network, ideally next to the sensor collecting the data, and has led to our smart systems becoming more and more connected. These systems need to process ever-increasing amounts of data, while at the same time being low-power, area-efficient and able to interact with the outside world in real time. There is therefore a need to explore unconventional hardware solutions that can meet these stringent requirements.
Brain-inspired architectures, in particular Spiking Neural Networks (SNNs), are promising candidates for achieving low-latency computation and stateful, energy-efficient operations. However, their current implementations are primarily based on digital or mixed-signal complementary metal-oxide-semiconductor (CMOS) technologies, which pose challenges in meeting the demanding memory, area and power constraints of edge computing. In addition, the implementation of multi-timescale dynamics in CMOS technology is extremely challenging and comes at the cost of a non-negligible increase in circuit complexity and area. Indeed, multi-timescale dynamics is shown by advanced learning theories to be essential in cognitive systems because it enables the system to react quickly, e.g. to avoid an object on a collision course or to detect an epileptic seizure, and to adapt to slow changes, e.g. ageing or wear of mechanical parts.
In this context, emerging memory technology, with its unique characteristics and capabilities, holds great promise for the design of such cognitive systems. Emerging memory devices are nanoscale devices that can change their conductivity when exposed to appropriate electrical stimuli. They offer fast and energy-efficient tunable volatile and non-volatile memory and are therefore well suited for storing SNN parameters. Exploiting their unique properties, such as operating voltages compatible with current CMOS technology and analogue neural/synaptic-like behaviour, offers an attractive opportunity to realise energy-efficient and massively parallel computing architectures. Indeed, if properly combined with CMOS technology, these features can extend the functionality of current artificial intelligence (AI) systems, enabling efficient computation, neural dynamics and synaptic plasticity, which are essential features for emulating the functionality of the brain in hardware. However, achieving this goal is still an open challenge at several levels, from device fabrication to integration with circuitry and architecture.
Objectives of MEMRINESS
The aim of the MEMRINESS project is to create new fundamental computing primitives that will overcome the current challenges for the deployment of intelligent systems at the edge. At the core of MEMRINESS is the development of neurons and synapses that exploit the intrinsic physical properties and dynamics of emerging volatile and non-volatile memory devices to enable the design of compact, power-efficient SNNs with multi-timescale dynamics.
The design of high-performance hardware AI systems relies on the synergistic development of emerging memory devices, circuits and learning algorithms. This approach requires system-technology co-optimisation (STCO) of emerging memory devices and CMOS circuits to enable seamless integration and exploit the strengths of both technologies. Indeed, the co-design of devices, circuits and algorithms requires the identification and resolution of issues related to device variability, scalability and system integration. Through the synergistic co-development of memristive devices, CMOS circuits and innovative algorithms, MEMRINESS will pave the way for intelligent edge systems capable of performing complex cognitive tasks.
The work and main achievements of the first period are described below. The main focus of this period is on Objectives 1&2.
Objective 1 - Development of fundamental memristive devices, learning algorithms, and circuits.
Devices - We fabricated and characterised ferroelectric-based capacitors (FeCap). We developed a compact model for the inclusion of FeCap elements in circuit simulation. In parallel, the already existing Juelich Aachen Resistive Switching Tools (JART) model for non-volatile resistive switching devices (ReRAM) has been studied and included in circuit simulations.
Circuits - We designed integrated circuits to characterise emerging memory devices and evaluate their fabrication process. In addition, circuits able to exploit emerging memory dynamics were also conceived.
Algorithms - Using the JAX framework, we developed a model simulation environment to test different learning rules that take into account the non-idealities of the devices. Moreover, the multi-timescale learning rule, known as “two-phase plasticity” was selected as the target algorithm to implement in hardware.
Objective 2 - Development of memristive neurons and synapses for neuromorphic edge computing.
We designed a leaky integrate-and-fire neuron based on a mixed FeCap-CMOS technology (FeLIF), fully leveraging the capabilities of both technologies. The fully CMOS version of the multi-timescale synapse is also designed.
Objective 3 - Demonstration of memristive neurons and synapses in collaborative SNNs on the edge.
This objective is going to be the focus of the last part of the project. We are now conducting preliminary studies to replicate the behaviour of the hardware neurons and synapses on a Phyton code to enable network-level simulations.
Objective 1 - Development of fundamental memristive devices, learning algorithms, and circuits.
Devices - We fabricated and characterised ferroelectric-based capacitors (FeCap). We developed a compact model for the inclusion of FeCap elements in circuit simulation. In parallel, the already existing Juelich Aachen Resistive Switching Tools (JART) model for non-volatile resistive switching devices (ReRAM) has been studied and included in circuit simulations.
Circuits - We designed integrated circuits to characterise emerging memory devices and evaluate their fabrication process. In addition, circuits able to exploit emerging memory dynamics were also conceived.
Algorithms - Using the JAX framework, we developed a model simulation environment to test different learning rules that take into account the non-idealities of the devices. Moreover, the multi-timescale learning rule, known as “two-phase plasticity” was selected as the target algorithm to implement in hardware.
Objective 2 - Development of memristive neurons and synapses for neuromorphic edge computing.
We designed a leaky integrate-and-fire neuron based on a mixed FeCap-CMOS technology (FeLIF), fully leveraging the capabilities of both technologies. The fully CMOS version of the multi-timescale synapse is also designed.
Objective 3 - Demonstration of memristive neurons and synapses in collaborative SNNs on the edge.
This objective is going to be the focus of the last part of the project. We are now conducting preliminary studies to replicate the behaviour of the hardware neurons and synapses on a Phyton code to enable network-level simulations.
The FeCap compact model is a big step forward. The model has been developed to enable circuit simulations for STCO and uses a comprehensive physics-based approach.
On the circuit side, the FeCap model enabled the design of the FeLIF neuron thanks to its accurate representation of the device's dynamics.
The FeLIF's two time constants, made possible by the FeCap, add functionality and make the design more compact. The current spike mode used to drive the circuits is typical in CMOS bio-plausible hardware but new for FeCaps.
On the circuit side, the FeCap model enabled the design of the FeLIF neuron thanks to its accurate representation of the device's dynamics.
The FeLIF's two time constants, made possible by the FeCap, add functionality and make the design more compact. The current spike mode used to drive the circuits is typical in CMOS bio-plausible hardware but new for FeCaps.