Periodic Reporting for period 1 - ANIMATE (ANalogue In-Memory computing with Advanced device TEchnology)
Período documentado: 2023-05-01 hasta 2025-10-31
Every day we generate, process and use a massive amount of data. Searching a keyword on the internet, choosing a movie for the weekend and booking our next holiday are just a few simple actions that rely on data-intensive algorithms in the cloud, such as data search, recommendation and page ranking. The energy cost of computation is high: it has been recently reported that training a relatively large neural network produces the same carbon dioxide of 5 cars in their whole lifetime. Data centres use an estimated 200 terawatt-hours each year, corresponding to 1% of the global demand. With the spectre of an energy-hungry future, it is essential to identify novel concepts, novel algorithms and novel hardware for streamlining the computing process.
My preliminary research has shown that computing energy requirements can be reduced by closed-loop in-memory computing (CL-IMC) that can solve linear algebra problems in just one computational step. In CL-IMC, the time to solve a certain problem does not increase with the problem size, in contrast to other computing concepts, such as digital and quantum computers. Thanks to the size-independent computing time around 100 ns, CL-IMC requires 5,000 times less energy than top-class digital computers at the same bit precision. These preliminary results show that CL-IMC is a promising new computing concept to reduce the energy consumption of data processing.
My project will develop the device technology, the circuit topologies, the system-level architectures and the application portfolio to fully validate the CL-IMC concept. A novel memory technology that is immune to wire resistance effects will be developed. CL-IMC integrated circuits will be designed with standard CMOS technology. System-level architecture and application exploration will further support the scalability and feasibility of the concept, to demonstrate CL-IMC as a primary contender among the computing technologies with improved energy efficiency.
My preliminary research has shown that computing energy requirements can be reduced by closed-loop in-memory computing (CL-IMC) that can solve linear algebra problems in just one computational step. In CL-IMC, the time to solve a certain problem does not increase with the problem size, in contrast to other computing concepts, such as digital and quantum computers. Thanks to the size-independent computing time around 100 ns, CL-IMC requires 5,000 times less energy than top-class digital computers at the same bit precision. These preliminary results show that CL-IMC is a promising new computing concept to reduce the energy consumption of data processing.
My project will develop the device technology, the circuit topologies, the system-level architectures and the application portfolio to fully validate the CL-IMC concept. A novel memory technology that is immune to wire resistance effects will be developed. CL-IMC integrated circuits will be designed with standard CMOS technology. System-level architecture and application exploration will further support the scalability and feasibility of the concept, to demonstrate CL-IMC as a primary contender among the computing technologies with improved energy efficiency.
At the end of the first reporting period, the project has achieved several groundbreaking results about the development of advanced memories and the design of new circuits for closed-loop in-memory computing.
In WP1, MoS2-based charge trap memory (CTM) devices were developed and optimized for CL-IMC in terms of on-off ratio, histeresis loop and retention time constant. A novel reservoir computing circuit with MoS2-based CTM was developed, allowing for epileptic seizure detection. 3D-VRRAM devices were also demonstrated with precise multilevel operation for IMC.
In WP2, novel program scheme were developed to enable precise mulilevel operation and drift compensation by mapping differential weights in phase change memory.
In WP3, novel circuits were designed for generalized block matrix mapping of algebra problems, as well as eigendecomposition for principal component analysis.
In WP4, new architectures to scale up the density of CL-IMC systems are currently being explored.
In WP5, new applications of CL-IMC circuits were addressed, namely massive multiple-in/multiple-out (MIMO) signal processing for wireless communication and Kalman filters for autonomous navigation and mobility.
In WP1, MoS2-based charge trap memory (CTM) devices were developed and optimized for CL-IMC in terms of on-off ratio, histeresis loop and retention time constant. A novel reservoir computing circuit with MoS2-based CTM was developed, allowing for epileptic seizure detection. 3D-VRRAM devices were also demonstrated with precise multilevel operation for IMC.
In WP2, novel program scheme were developed to enable precise mulilevel operation and drift compensation by mapping differential weights in phase change memory.
In WP3, novel circuits were designed for generalized block matrix mapping of algebra problems, as well as eigendecomposition for principal component analysis.
In WP4, new architectures to scale up the density of CL-IMC systems are currently being explored.
In WP5, new applications of CL-IMC circuits were addressed, namely massive multiple-in/multiple-out (MIMO) signal processing for wireless communication and Kalman filters for autonomous navigation and mobility.
After the first reporting period, the CL-IMC concepts confirms the strong advantages in terms of reduced energy consumption and lower cost of implementation, thanks to the high density of the memory devices and the reduced data movement. The potential impact of the project directly stems from the ability to accelerate inverse problems, such as matrix inversion and pseudoinversion, which generally constitute the computational bottleneck of several engineering tasks, such as wireless communication, robotic inverse kinematics and autonomous navigation. At the same time, significant challenges have emerged and are currently being addressed via various multidisciplinary approaches and strategic collaborations. A notable challenge is the medium-low precision of the memory device and the inability to compete with state-of-the-art digital computing systems with floating-point precision. This challenge needs to be handled from two standpoints: on the one side, the identification of suitable application fields where a medium-low prevision of computation is acceptable. On the other hand, identify strategies, architectures and algorithms capable of upgrading the precision of CL-IMC by error correction and compensation techniques. This might be the topic of further development and demonstration activities.