The technical objectives of the project were achieved with the help of three work packages WP1, WP2 and WP3.
WP1 was designed to determine an optimal power architecture for driving the eVTOL motors from the battery packs. This involved the study of various eVTOLs, their energy system specification, dc bus voltage ratings and power converter architecture. An analytical model of the power loss of SiC devices used in the power converter along with the analytical model for power cable weight as a function of the dc bus was developed. This was used to formulate an objective function to solve the optimization problem. The result was a recommendation on the dc bus voltage beyond the state-of-the-art. Considering the mission profile of eVTOLs, it was observed that the torque and speed requirements for the drive motors are highest during takeoff and landing. They are lowest during cruise mode, which is the longest period in the eVTOL mission. This led to the development of a reconfigurable power architecture that regulates the dc bus voltage electronically depending on the flight mission. The maximum voltage available is remains high to ensure reduced cable weight due to reduced current ratings for a given power. The proposed optimal power architecture facilitates an interaction between the battery management system (BMS) and flight control computer (FCC) that is beneficial in maximizing the power conversion efficiency, enhancing battery lifetime, and improving safety through enhanced battery diagnostics.
WP2 aimed to develop the smart BMS hardware and algorithms to estimate battery states such as SoH and SoC accurately, with a target peak error of 1% or lower. The algorithms preferred in the WP were primarily machine learning (ML) based since Li-ion batteries are complex to model. Multiple versions of the smart BMS hardware were designed and developedwith different test environments. For example, the first set of hardware was designed to be compatible with a 96-cell battery simulator setup from Comemso, which is a commercial manufacturer of battery simulators. This was done to ensure that the state estimation and BMS algorithms are tested safely in a laboratory environment before deploying them on BMS working with real cells. The second set of hardware was cell-level BMS for prismatic cells of different capacity and chemistry. One was for Nickel-Manganese-Cobalt Oxide (NMC) cells with 50Ah capacity and the second was for Lithium Iron Phosphate (LFP) cells with 100Ah capacity. The developed hardware addressed the challenges of minimizing power loss, printed circuit board (PCB) packaging and involved an enhanced gate driver design. A study on various communication protocols was performed. The BMS hardware was designed with wireless communication. The study concluded with the recommendation to use IEEE time slotted channel hopping (TSCH) protocol due to its robustness and fault tolerance while serving a large number of communication nodes. This communication protocol was implemented in the microcontroller hardware.
In WP2, a novel approach was developed to obtain the Li-ion equivalent circuit model (ECM) parameters online using discrete impedance values. This resulted in a fast and low-complexity computation method that can be implemented even in a conventional BMS. This modelling approach led to the development of an accurate battery digital twin (BDT) that can be used in BMS for enhancing safety by faster fault prediction and corrective action. The proposed ECM parameter estimation method was used to extract features for the ML algorithms. Two methods were developed for SoH and SoC estimation using ML. The first method prioritized low-complexity online implementation and achieved peak errors lower than 2%. This method used linear regression-based algorithm with ECM parameters evaluated online in the smart BMS. The second method used feed forward neural networks for improving the accuracy and reducing the peak errors to within 1%.
The WP3 was designed to include the hardware realization of the smart BMS and the proposed power architecture for the SiC based eVTOL drive train power converter. The smart BMS hardware was designed, fabricated, and tested experimentally. Thermal performance of the PCB was verified experimentally to ensure that the semiconductor devices in the BMS have minimal temperature rise meeting the design specifications. The wireless communication software was implemented in the microcontroller used in the smart BMS and it was validated experimentally. A simplified SoC balancing method was implemented to verify the performance of the master-slave communication architecture and the lossless balancing due to the embedded half-bridge circuit in the smart BMS.
In WP3, a SiC based drive inverter hardware was setup. This scaled down prototype was tested to validate the analytical models developed to optimize the power converter architecture. A high voltage regulated variable dc supply was used to emulate the electronic reconfiguration of the dc bus voltage in the proposed architecture. The experimental setup developed was along with a dSpace-based pulse width modulation (PWM) controller. For the full-power-rated system, the EMI performance was verified in simulation since full scale EMI filter size minimization objective aligned with this WP. It was observed that a 2-level inverter, used conventionally, requires large EMI filters due to the stringent commercial standards for aerospace applications. As a result, a multi-level inverter topology was chosen which minimizes the EMI filter requirement without significantly impacting cost or complexity of the power converter architecture.
The work done in the project has resulted in multiple journals, conferences, tutorials, and poster presentations
