Periodic Reporting for period 1 - ACROBAT (Hardware Acceleration with Tunable SRAM/IMC Voltages)
Reporting period: 2023-09-01 to 2025-05-31
In this project, an automatic memory design framework employing a specialized SRAM with tunable voltage levels is proposed to reduce energy consumption and alleviate the search complexity of the design space. The study is then planned to be extended to the emerging in-memory computing (IMC) design and suggests a solution to solve the common SNR and robustness problems in this research area. The framework outputs the optimal set of memory configurations for a given DNN workload. It accounts for the integration of different algorithmic optimizations while balancing the accuracy and the SRAM/IMC energy consumption and fault rates with reconfigurable weight precision. This improvement is important as IMC design is considered one of the most promising approaches to energy efficiency in the edge-AI era, where there is high demand both in industry and academia to come up with innovative, robust architectures, and power-efficient end products. [The implementation is not completed due to the early termination of the project (end of work date on January 12, 2024).]
The initial stage of the project was building memory power models with bit-error-rates (BERs). Since this step requires building infrastructure for empirical and/or analytical estimation of power models using design kits/tools of a specific technology (which was going to be accessible after the necessary paperwork has been completed by the university and the non-academic placement company), the implementation of the simulation framework was prioritized. The details of the work done so far is summarized below:
Optimization Stage 1
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At this stage, each layer is optimized for pruning of filters, assignment of separate quantization levels and voltage values for each (1) output channel, (2) input channel and (3) filter in the layer.
Optimization Stage 2
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The simulation framework focuses on minimizing the data movement cost across different memory hierarchies and construction of an optimization framework that finds an optimal value for the number of SRAM partitions/blocks and corresponding voltage assignments.
At its core, it involves a few key components: Convolution Simulation, Cache Management (stores tiles of data and has a fixed total size, partitioned into a fixed number of segments each associated with a specific voltage assignment), Cost Calculation (the movement of data between cache and DRAM), Configuration Optimization (to find the loop order and voltage assignment of cache partitions with minimum data movement cost).
Optimization Stage 1
======================
At this stage, each layer is optimized for pruning of filters, assignment of separate quantization levels and voltage values for each (1) output channel, (2) input channel and (3) filter in the layer.
Optimization Stage 2
======================
The simulation framework focuses on minimizing the data movement cost across different memory hierarchies and construction of an optimization framework that finds an optimal value for the number of SRAM partitions/blocks and corresponding voltage assignments.
At its core, it involves a few key components: Convolution Simulation, Cache Management (stores tiles of data and has a fixed total size, partitioned into a fixed number of segments each associated with a specific voltage assignment), Cost Calculation (the movement of data between cache and DRAM), Configuration Optimization (to find the loop order and voltage assignment of cache partitions with minimum data movement cost).