The initial stage of the project was building memory power models with bit-error-rates (BERs). Since this step requires building infrastructure for empirical and/or analytical estimation of power models using design kits/tools of a specific technology (which was going to be accessible after the necessary paperwork has been completed by the university and the non-academic placement company), the implementation of the simulation framework was prioritized. The details of the work done so far is summarized below:
Optimization Stage 1
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At this stage, each layer is optimized for pruning of filters, assignment of separate quantization levels and voltage values for each (1) output channel, (2) input channel and (3) filter in the layer.
Optimization Stage 2
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The simulation framework focuses on minimizing the data movement cost across different memory hierarchies and construction of an optimization framework that finds an optimal value for the number of SRAM partitions/blocks and corresponding voltage assignments.
At its core, it involves a few key components: Convolution Simulation, Cache Management (stores tiles of data and has a fixed total size, partitioned into a fixed number of segments each associated with a specific voltage assignment), Cost Calculation (the movement of data between cache and DRAM), Configuration Optimization (to find the loop order and voltage assignment of cache partitions with minimum data movement cost).
