Secure Hardware with AdvaNced NONvolatile memories

Informations projet

SHANNON

N° de convention de subvention: 101069299

DOI

10.3030/101069299

Projet clôturé

Date de signature de la CE 29 Juillet 2022

Date de début 1 Novembre 2022

Date de fin 30 Avril 2024

Financé au titre de

• European Research Council (ERC)

Coût total

Aucune donnée

Contribution de l’UE

€ 150 000,00

Coordonné par

POLITECNICO DI MILANO
Italy

Periodic Reporting for period 1 - SHANNON (Secure Hardware with AdvaNced NONvolatile memories)

Période du rapport: 2022-11-01 au 2024-04-30

Résumé du contexte et des objectifs généraux du projet

Over the recent years, the explosive growth of digital technologies allowed to implement disruptive business models driven by data collection and processing. In particular, the internet of things (IoT), where massive number of “things” (sensors, actuators, drones, etc.) interact with the environment and with each other, unlocks a significant value for consumers (smart society), organisations/companies (industry 4.0/ smart factories) and governments (smart nations). However, as every adoption of new technologies involves some risks, security attacks are today one of the biggest challenges for IoT. The overall inflicted damages of cybercrime in 2021, in fact, have an estimated total of $6 trillion which makes Cybercrime one of the world’s largest economy comparable to U.S. and China. Security of IoT is generally enabled by the physical unclonable function (PUF), namely a hardware function which is embedded in the chip and capable of generating a random response to a given challenge. Recently, PUFs based on emerging nonvolatile memory have attracted a strong interest thanks to their high scalability, high density, low cost and good integration with CMOS technology. However, NVM with high resistance to tampering and high reliability to temperature variations are not available yet.
The objective of this project is to demonstrate the feasibility of an invisible PUF (iPUF) based on a nonvolatile memory with stochastic states which cannot be identified externally from optical or magnetic microsensors. The iPUF relies on (i) a stochastic nonvolatile memory technology, (ii) an efficient algorithm capable of generating a PUF response from an applied challenge with high reliability to temperature variations and resistance to tampering.

Travail effectué depuis le début du projet jusqu’à la fin de la période considérée dans le rapport et principaux résultats atteints jusqu’à présent

The project was able to support the feasibility of iPUF based on a stochastic phase change memory (PCM) in the virgin state. Due to the thermal budget during the fabrication process, the chalcogenide layer in the PCM can show segregation of different phases, such as crystalline Ge grains in the case of Ge-rich Ge2Sb2Te5. These grains are characterized by stochastic variation of size and position, resulting in a large spread of conductance that can be exploited as a stochastic entropy source for the PUF. In the Shannon project, we have developed a physics-based model (result #1 of the project) of the virgin PCM to predict the statistical distribution of conductance, the dependence on temperature and the dependence on the applied read voltage. The model was used to run Monte Carlo simulations of the PUF to assess the figure of metric of a PCM-based PUF where the PUF challenge serves as address of input cells, while the PUF response consists of the measured output of a readout circuit and suitable analog/digital processing which ensures maximum reliability and compliance with the NIST test suite. The virgin PCM technology was used as a preferred technology to support the proof- of-concept of the new PUF. To support the PCM-based PUF concept, we have designed a PUF prototype (result #2 of the project) in a CMOS 90nm technology including a PCM array, row/column decoders, analogue comparator for differential sensing and digital circuit for challenge pre-processing and response generation. The mixed analogue/digital integrated circuit was design and fabricated with an industrial CMOS 90 nm technology to support the feasibility and maturity of our PUF technology. To enable high reliability against temperature variations, a new circuit and algorithm was developed and patented (result #3 of the project). The new solutions is capable to suppress the bit error rate due to temperature variations by more than two orders of magnitude.

Progrès au-delà de l’état des connaissances et impact potentiel prévu (y compris l’impact socio-économique et les conséquences sociétales plus larges du projet jusqu’à présent)

The project has overall provided support to the feasibility of the memory-based iPUF technology based on three main results, spanning the methodology, the modeling and the prototyping of PUF integrated circuits.
The first result beyond the state of the art is a new model for the conductance distribution in virgin-state phase change memory array. The new model allows to predict the distribution of conductance and its dependence on temperature for the memory array in the virgin state thus enabling PUF and other computing primitives. The simulation model is illustrated in part in a publication for the purpose of dissemination and potential exploitation.
The second result beyond the state of the art is an integrated circuit for the computation of a physical unclonable function from a stochastic memory array. The circuit provides a proof-of-concept of a memory-based PUF for highly-scalable integrated hardware security and cryptographic key generation. The circuit has been prototyped in a production environment by manufacturing in CMOS technology by industrial partner STMicroelectronics. A printed circuit board is currently under development for pilot, demonstration and testing activities, as well as for a feasibility study of the overall methodology, including in-memory computing within the chip and enrolment of a key-book at various temperatures. The circuit was designed in 90 nm technology and includes a phase change memory (PCM) array, a row/column decoder, analog comparators for the read current and digital blocks for generating the PUF response
The third result beyond the state of the art is novel methodology for stabilizing the PUF against temperature-induced variations. The new methodology adopts a new circuit and a new enrolment procedure to stabilize the PUF based on memory devices with respect to temperature. Currently, this methodology is under prototyping in a laboratory environment. IPR has also been managed by the deposition of an Italian patent, which will be followed by extension to an international patent.
Dissemination of these results has been pursued via (i) a journal paper publication and (ii) presentation in various international venues and potential industry partners.
Exploitation of the project results has been extensively addressed by (i) market and sector snapshot, (ii) identification of the most suitable industrial and institutional stakeholders, and (iii) elaboration of an exploitation plan. Further uptake of these results to maximize their impact will require IPR management, such as patent extension, and demonstration activities with the developed prototype in industrial application domains, to approach potential licensees and strategic partners.

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