Periodic Reporting for period 1 - SPIDER (Computation Systems Based on Hybrid Spin-wave–CMOS Integrated Architectures)
Reporting period: 2022-12-01 to 2024-05-31
The ambition of SPIDER is to bring SW computing to a demonstrator at TRL 5 by designing and realising a hybrid SW–CMOS computing system that interfaces with standard microelectronics.
The detailed objectives of SPIDER are as follows:
O1: Demonstrate a hybrid SW–CMOS computing system: computation occurs via SW interference while input and output interfaces are implemented with conventional CMOS and microelectronic systems.
O2: Develop, design, and realise a SW circuit beyond a single MAJ3.
O3: Develop, design, and realise a mixed signal CMOS APIC to drive and read out the SW circuit.
O4: Develop, design, and realise a large bandwidth RF interposer to co-integrate the mixed signal CMOS APIC and the SW circuit into a single package.
O5: Co-optimise the technology of SW circuit, periphery CMOS circuit, and interposer to obtain a single operational system (STCO).
The detailed objectives of SPIDER are as follows:
O1: Demonstrate a hybrid SW–CMOS computing system: computation occurs via SW interference while input and output interfaces are implemented with conventional CMOS and microelectronic systems.
O2: Develop, design, and realise a SW circuit beyond a single MAJ3.
O3: Develop, design, and realise a mixed signal CMOS APIC to drive and read out the SW circuit.
O4: Develop, design, and realise a large bandwidth RF interposer to co-integrate the mixed signal CMOS APIC and the SW circuit into a single package.
O5: Co-optimise the technology of SW circuit, periphery CMOS circuit, and interposer to obtain a single operational system (STCO).
Recent interest in spintronic devices for electronic applications has grown, including their use in neuromorphic computation and analog data processing. SPIDER focuses on a subset of spintronic devices using spin waves (SW), i.e. precession excitations in ferromagnetic media. The benchmarking data show that these devices bear potential for ultra-low power electronics or compact analogue RF devices. However, to date, practical commercial applications remain distant.
Demonstration of several proof-of-concept devices with SW for computing applications have so far been performed exclusively at the laboratory level, using probe stations or simple packaging alongside benchtop measurement systems like vector-network analysers (VNAs), or even large-scale optical setups. As a result, all proof-of-concept realizations have been confined to the single-device level, with more complex SW circuits and systems remaining elusive.
SPIDER aims to bridge the gap by developing hybrid spin-wave-CMOS systems that use SW for computation, driven by electrical signals, and can be integrated into standard microelectronic devices. The project focuses on creating an arithmetic 8-bit adder circuit, where logic operations are performed in the SW domain while data exchange and gate cascading are managed through a CMOS circuit.
The SPIDER project requires the design and development—and ultimately the integration—of three independent components to achieve the final objective of a hybrid spin-wave-CMOS system: the SW chip, the mixed signal periphery chip (APIC), and the interposer to combine the two chips. These components require expertise from various scientific and technological domains that do not typically overlap.
In the first part of the project, the initial major task of SPIDER was to establish a common foundation for the involved experts from diverse backgrounds. SPIDER has invested significant effort and time in knowledge exchange to ensure that all consortium members could contribute their expertise as efficiently as possible.
Building on this collective understanding, SPIDER has initiated the system-technology co-design of the individual components and the entire system. Previously, SW logic research primarily followed a laboratory approach, focusing on measuring individual devices and reporting semiquantitative data, such as spectral information about SW transmission, without much emphasis on absolute transmitted power levels. One of the major challenges for SPIDER has been the lack of essential data, such as absolute load impedances, self-inductances of logic gates, or device-to-device variability. SPIDER has made significant progress in this area, particularly in understanding transducer (antenna) impedances and transmitted power levels.
As detailed in the first technical interim report, the primary material options for the ferromagnetic SW host material were CoFeB and Y3Fe5O12 (YIG). Based on the System-Technology Co-Design (STCD) document elaborated by SPIDER, YIG was chosen to start with due to its long SW attenuation length.
The SW chip design has been translated into a photolithography mask set, ensuring that RF port positions are compatible with APIC and interposer designs. This compatibility requirement imposed certain design rules on the MG. The initial design was based on patterned YIG waveguides, but achieving low-defect YIG etching has proven challenging, as detailed in WP4. Measurements have found, however, that device-to-device cross-talk levels are low even in extended, unpatterned YIG films. Consequently, SPIDER has decided to use unpatterned YIG films for the MGs rather than patterned waveguides, reducing processing complexity without compromising device performance.
Nonetheless, the design rules have resulted in a suboptimal antenna design compared to the antennas used in the transmission line experiments, increasing insertion losses. A redesign of second-generation MGs is anticipated to address this issue, leading to signal levels compatible with APIC-controlled operation. This redesign has been finished at the time of writing.
In parallel, SPIDER has collaboratively designed the necessary peripheral circuitry to drive SWMGs using digital voltage signals. These activities were built on the shared understanding developed from the project's objectives. The goal of designing the Analog Periphery IC (APIC) was to ensure functionality, even at the expense of performance. As reported in WP3, SPIDER has finalized the design of the first-generation APIC, which can drive individual SWMGs. A second-generation APIC will be developed in the latter part of the project, incorporating lessons learned from the first generation. This upgraded APIC will enable gate cascading and will be used to drive the complete 8-bit adder system.
Concerning the final system, SPIDER has decided to pursue an 8-bit Brent-Kung adder. First circuit SW designs have been created and the circuit complexity has been studied. The results indicate that the complexity of such a system is high, but not too high to be realized in a hybrid spin-wave-CMOS system.
Regarding the initial project scheduling, the tape-out of the APIC was delayed due to the complexity of the task. Initially planned for December 2023, the APIC tape-out has occurred in March 2024, as expected from the updated schedule reported in the first technical interim report. The APICs have been delivered in June 2024 and are now available for packaging.
The third key component of the final hybrid system is the interposer, which combines the SW chip and the APIC into a single package, developed in WP5. Initial interposer designs, which routed microwave signals, revealed potential issues with phase control in the final system. Consequently, SPIDER is now primarily pursuing the cascading of SWMG in the APIC using low-frequency voltage signals to ensure successful operation over performance.
Before fabricating the full system, intermediate packaging solutions are necessary and have been developed by SPIDER. An evaluation board has been created that can be combined with the APIC to assess its performance. Additionally, SPIDER has designed an RF interposer that can be integrated with the SW chip to evaluate the RF performance of the combined system. This allows for a detailed understanding of the RF circuit, including the interposer and SWMGs, as seen by the APIC at its RF inputs and outputs.
Demonstration of several proof-of-concept devices with SW for computing applications have so far been performed exclusively at the laboratory level, using probe stations or simple packaging alongside benchtop measurement systems like vector-network analysers (VNAs), or even large-scale optical setups. As a result, all proof-of-concept realizations have been confined to the single-device level, with more complex SW circuits and systems remaining elusive.
SPIDER aims to bridge the gap by developing hybrid spin-wave-CMOS systems that use SW for computation, driven by electrical signals, and can be integrated into standard microelectronic devices. The project focuses on creating an arithmetic 8-bit adder circuit, where logic operations are performed in the SW domain while data exchange and gate cascading are managed through a CMOS circuit.
The SPIDER project requires the design and development—and ultimately the integration—of three independent components to achieve the final objective of a hybrid spin-wave-CMOS system: the SW chip, the mixed signal periphery chip (APIC), and the interposer to combine the two chips. These components require expertise from various scientific and technological domains that do not typically overlap.
In the first part of the project, the initial major task of SPIDER was to establish a common foundation for the involved experts from diverse backgrounds. SPIDER has invested significant effort and time in knowledge exchange to ensure that all consortium members could contribute their expertise as efficiently as possible.
Building on this collective understanding, SPIDER has initiated the system-technology co-design of the individual components and the entire system. Previously, SW logic research primarily followed a laboratory approach, focusing on measuring individual devices and reporting semiquantitative data, such as spectral information about SW transmission, without much emphasis on absolute transmitted power levels. One of the major challenges for SPIDER has been the lack of essential data, such as absolute load impedances, self-inductances of logic gates, or device-to-device variability. SPIDER has made significant progress in this area, particularly in understanding transducer (antenna) impedances and transmitted power levels.
As detailed in the first technical interim report, the primary material options for the ferromagnetic SW host material were CoFeB and Y3Fe5O12 (YIG). Based on the System-Technology Co-Design (STCD) document elaborated by SPIDER, YIG was chosen to start with due to its long SW attenuation length.
The SW chip design has been translated into a photolithography mask set, ensuring that RF port positions are compatible with APIC and interposer designs. This compatibility requirement imposed certain design rules on the MG. The initial design was based on patterned YIG waveguides, but achieving low-defect YIG etching has proven challenging, as detailed in WP4. Measurements have found, however, that device-to-device cross-talk levels are low even in extended, unpatterned YIG films. Consequently, SPIDER has decided to use unpatterned YIG films for the MGs rather than patterned waveguides, reducing processing complexity without compromising device performance.
Nonetheless, the design rules have resulted in a suboptimal antenna design compared to the antennas used in the transmission line experiments, increasing insertion losses. A redesign of second-generation MGs is anticipated to address this issue, leading to signal levels compatible with APIC-controlled operation. This redesign has been finished at the time of writing.
In parallel, SPIDER has collaboratively designed the necessary peripheral circuitry to drive SWMGs using digital voltage signals. These activities were built on the shared understanding developed from the project's objectives. The goal of designing the Analog Periphery IC (APIC) was to ensure functionality, even at the expense of performance. As reported in WP3, SPIDER has finalized the design of the first-generation APIC, which can drive individual SWMGs. A second-generation APIC will be developed in the latter part of the project, incorporating lessons learned from the first generation. This upgraded APIC will enable gate cascading and will be used to drive the complete 8-bit adder system.
Concerning the final system, SPIDER has decided to pursue an 8-bit Brent-Kung adder. First circuit SW designs have been created and the circuit complexity has been studied. The results indicate that the complexity of such a system is high, but not too high to be realized in a hybrid spin-wave-CMOS system.
Regarding the initial project scheduling, the tape-out of the APIC was delayed due to the complexity of the task. Initially planned for December 2023, the APIC tape-out has occurred in March 2024, as expected from the updated schedule reported in the first technical interim report. The APICs have been delivered in June 2024 and are now available for packaging.
The third key component of the final hybrid system is the interposer, which combines the SW chip and the APIC into a single package, developed in WP5. Initial interposer designs, which routed microwave signals, revealed potential issues with phase control in the final system. Consequently, SPIDER is now primarily pursuing the cascading of SWMG in the APIC using low-frequency voltage signals to ensure successful operation over performance.
Before fabricating the full system, intermediate packaging solutions are necessary and have been developed by SPIDER. An evaluation board has been created that can be combined with the APIC to assess its performance. Additionally, SPIDER has designed an RF interposer that can be integrated with the SW chip to evaluate the RF performance of the combined system. This allows for a detailed understanding of the RF circuit, including the interposer and SWMGs, as seen by the APIC at its RF inputs and outputs.
It is too early for the first reporting period to discuss about needs for further uptake and success beyond the end of the project at this stage.