Periodic Reporting for period 2 - SPIDER (Computation Systems Based on Hybrid Spin-wave–CMOS Integrated Architectures)
Okres sprawozdawczy: 2024-06-01 do 2025-05-31
The ambition of SPIDER is to bring SW computing to a demonstrator at TRL 5 by designing and realising a hybrid SW–CMOS computing system that interfaces with standard microelectronics.
The detailed objectives of SPIDER are as follows:
O1: Demonstrate a hybrid SW–CMOS computing system: computation occurs via SW interference while input and output interfaces are implemented with conventional CMOS and microelectronic systems.
O2: Develop, design, and realise a SW circuit beyond a single MAJ3.
O3: Develop, design, and realise a mixed signal CMOS APIC to drive and read out the SW circuit.
O4: Develop, design, and realise a large bandwidth RF interposer to co-integrate the mixed signal CMOS APIC and the SW circuit into a single package.
O5: Co-optimise the technology of SW circuit, periphery CMOS circuit, and interposer to obtain a single operational system (STCO).
The detailed objectives of SPIDER are as follows:
O1: Demonstrate a hybrid SW–CMOS computing system: computation occurs via SW interference while input and output interfaces are implemented with conventional CMOS and microelectronic systems.
O2: Develop, design, and realise a SW circuit beyond a single MAJ3.
O3: Develop, design, and realise a mixed signal CMOS APIC to drive and read out the SW circuit.
O4: Develop, design, and realise a large bandwidth RF interposer to co-integrate the mixed signal CMOS APIC and the SW circuit into a single package.
O5: Co-optimise the technology of SW circuit, periphery CMOS circuit, and interposer to obtain a single operational system (STCO).
During this period, SPIDER focused on fabricating the first hybrid spin-wave-CMOS systems based on the project’s original concepts. With system-technology co-design principles established, the team designed and fabricated the three core components of the final system: the magnetic spin-wave chip, the CMOS Analog Periphery IC (APIC), and the interposer.
As in the first period, SPIDER’s spin-wave chips use YIG (Yttrium Iron Garnet) for its long spin-wave attenuation length, which supports efficient device design and strong microwave signal coupling. Spin-wave majority gates were implemented using U-shaped microwave antennas as transducers, with antenna design optimized to reduce insertion loss. The design avoids YIG etching, minimizing defects and contributing to good device yield.
In the first reporting period, SPIDER developed the APIC—a CMOS-based driver for spin-wave majority gates. The first APIC version was finalized in early 2024 and manufactured by TSMC in the first half of that year. During the second period, an evaluation board was created to test APIC functionality. Board yields were as expected, and tests confirmed the APIC’s operational capability and performance.
A second-generation APIC was developed using insights from the first version. Only minor adjustments were needed, such as optimizing the frequency band through improved antenna design. This version was taped out in early 2025, and chips are now available. Evaluation boards are in production, with testing to begin shortly. Based on first-generation experience, performance risks are considered low.
To evaluate spin-wave chip performance via the interposer, deembedding boards were fabricated and tested using vector network analyzers. These tests showed that integrating the spin-wave chip into the interposer caused only minor changes in microwave characteristics, aligning with simulation results.
However, the yield of packaged hybrid boards—combining APIC and spin-wave chip on a single interposer—has been low. As a result, SPIDER has not yet demonstrated full functionality (i.e. APIC-based generation and detection of spin waves) on a single packaged board. A root cause analysis is underway, though the exact cause of the low yield remains unclear. A review of the interposer design found no errors, and further device cross-sectioning is ongoing. Notably, packaging either the APIC or spin-wave chip individually has not shown significant yield issues. However, the evaluation and deembedding boards for these components involve slightly different processing steps and board designs due to technical constraints.
To address yield challenges, SPIDER is also implementing a modular final application board design. This approach allows for pre-selection of functional subsystems before final assembly, potentially reducing yield-related risks. Details are provided in the WP5 technical discussion.
Despite hybrid board yield issues, SPIDER successfully demonstrated a hybrid system by connecting APIC evaluation boards to spin-wave chips using microwave cables instead of interposer-based connections. Measurements confirmed that this setup works and that the APIC can generate and detect spin waves with phase sensitivity. This result indicates no fundamental barriers to SPIDER’s approach beyond packaging yield. These findings have been submitted as a paper to the IEEE IEDM conference. Additional hybrid board fabrication is planned, pending root cause analysis outcomes.
Meanwhile, the design of the final application board for an 8-bit adder is nearly complete. Fabrication is scheduled for Q3/Q4 2025, allowing sufficient time for characterization before the project concludes.
SPIDER has also initiated discussions on how to exploit its results. The project has developed an interface between spin-wave devices (based on YIG or other ferromagnetic materials) and CMOS mixed-signal peripherals. If successful, the packaging strategy could enable compact hybrid systems in a single package. Magnetic field control may be added in collaboration with the M&MEMS project. While digital logic remains a challenging application, SPIDER sees promising opportunities in RF analog domains at higher TRLs. These will be explored further before the project ends.
All RP2 deliverables were submitted with a two-month review period. All milestones to date have been achieved.
As in the first period, SPIDER’s spin-wave chips use YIG (Yttrium Iron Garnet) for its long spin-wave attenuation length, which supports efficient device design and strong microwave signal coupling. Spin-wave majority gates were implemented using U-shaped microwave antennas as transducers, with antenna design optimized to reduce insertion loss. The design avoids YIG etching, minimizing defects and contributing to good device yield.
In the first reporting period, SPIDER developed the APIC—a CMOS-based driver for spin-wave majority gates. The first APIC version was finalized in early 2024 and manufactured by TSMC in the first half of that year. During the second period, an evaluation board was created to test APIC functionality. Board yields were as expected, and tests confirmed the APIC’s operational capability and performance.
A second-generation APIC was developed using insights from the first version. Only minor adjustments were needed, such as optimizing the frequency band through improved antenna design. This version was taped out in early 2025, and chips are now available. Evaluation boards are in production, with testing to begin shortly. Based on first-generation experience, performance risks are considered low.
To evaluate spin-wave chip performance via the interposer, deembedding boards were fabricated and tested using vector network analyzers. These tests showed that integrating the spin-wave chip into the interposer caused only minor changes in microwave characteristics, aligning with simulation results.
However, the yield of packaged hybrid boards—combining APIC and spin-wave chip on a single interposer—has been low. As a result, SPIDER has not yet demonstrated full functionality (i.e. APIC-based generation and detection of spin waves) on a single packaged board. A root cause analysis is underway, though the exact cause of the low yield remains unclear. A review of the interposer design found no errors, and further device cross-sectioning is ongoing. Notably, packaging either the APIC or spin-wave chip individually has not shown significant yield issues. However, the evaluation and deembedding boards for these components involve slightly different processing steps and board designs due to technical constraints.
To address yield challenges, SPIDER is also implementing a modular final application board design. This approach allows for pre-selection of functional subsystems before final assembly, potentially reducing yield-related risks. Details are provided in the WP5 technical discussion.
Despite hybrid board yield issues, SPIDER successfully demonstrated a hybrid system by connecting APIC evaluation boards to spin-wave chips using microwave cables instead of interposer-based connections. Measurements confirmed that this setup works and that the APIC can generate and detect spin waves with phase sensitivity. This result indicates no fundamental barriers to SPIDER’s approach beyond packaging yield. These findings have been submitted as a paper to the IEEE IEDM conference. Additional hybrid board fabrication is planned, pending root cause analysis outcomes.
Meanwhile, the design of the final application board for an 8-bit adder is nearly complete. Fabrication is scheduled for Q3/Q4 2025, allowing sufficient time for characterization before the project concludes.
SPIDER has also initiated discussions on how to exploit its results. The project has developed an interface between spin-wave devices (based on YIG or other ferromagnetic materials) and CMOS mixed-signal peripherals. If successful, the packaging strategy could enable compact hybrid systems in a single package. Magnetic field control may be added in collaboration with the M&MEMS project. While digital logic remains a challenging application, SPIDER sees promising opportunities in RF analog domains at higher TRLs. These will be explored further before the project ends.
All RP2 deliverables were submitted with a two-month review period. All milestones to date have been achieved.
It is too early for the first reporting period to discuss about needs for further uptake and success beyond the end of the project at this stage.