Periodic Reporting for period 1 - QUARC (Quantum resistant communications: Advance Learning in applied PQC Training)
Período documentado: 2022-09-01 hasta 2024-08-31
QUARC is a doctoral network in the area of postquantum cryptography (PQC).
The objective of the project is to investigate and implement PQC systems on state-of-the-art network systems to demonstrate a path forward towards full integration.
Therefore, several DCs are looking at PQC algorithms and the features that networked systems need to have enable in order to cope with the requirements of PQC solutions.
The project have produced in PR1 state-of-the-art results, including the first PQC demonstrations operating at >100 Gbit/s.
The objectives described in the DoA are three, and they are all are being achieved satisfactorily. In fact, we can state QUARC has become a focal point in Europe in the area of PQC and has spun different activities that expand beyond the core of QUARC. In the following lines we will present the three objectives; we will first provide an overview of how they are being achieved, and on the following section describing the work conducted within the WPs, a more detailed technical description is provided.
O1- To investigate and develop an integral understanding of PQC encryption and how to translate it to a micro-architecture suitable for hardware implementation
This objective is being achieved. The following aspects have been reached during the current reporting period:
• In-depth study of the different PQC algorithms and their building blocks
• Identification of suitable HW platforms for PQC implementation
• Transfer of PQC-algos into single-thread implementation codes for CPUs
• Initial work on transfer of PQC-algos into multi-thread implementation codes for GPUs
O2- To propose PQC implementations exploiting reconfigurable processors and yielding compatibility with existing networking solutions
This objective is being achieved. All implementations proposed in QUARC have been done employing commercially available reconfigurable processors, which can be used by any researcher worldwide. The following aspects have been reached during the current reporting period:
• Implementation of all standardized PQC algorithms on an onboard CPU for a line-rate network interface card
• Implementation of all standardized PQC algorithms employing ARM-based hardware accelerators as HW offloads in a line-rate network interface card
• Implementation of Kyber/Dilithium on a IoT processor unit (i.e. Jetson) at low speed (~1 Gbit/s)
At the moment of this report, the team has started working on converged cards, where ARM-based and GPU-based processors co-exists on the same network interface card.
O3- To develop high-speed PQC demonstrators highlighting the feasibility of in-line encryption resistant to quantum processors
This objective is being achieved. Some of the proposed implementations (See Objective 2) have been ported to high-speed demonstrators. The following aspects have been reached during the current reporting period:
• Demonstration of all PQC algorithms operating at ~100 Gbit/s
• Preliminary design of building block optimizations for ~200 Gbit/s operation
• Preliminary work on GPU off-loading for high-speed PQC operation
We all objectives set in the description of work will be achieved and extend the state-of-the-art in the scientific domain dramatically. As per periodic report 1, the results reported by QUARC have set the global benchmark in the field.
The objective of the project is to investigate and implement PQC systems on state-of-the-art network systems to demonstrate a path forward towards full integration.
Therefore, several DCs are looking at PQC algorithms and the features that networked systems need to have enable in order to cope with the requirements of PQC solutions.
The project have produced in PR1 state-of-the-art results, including the first PQC demonstrations operating at >100 Gbit/s.
The objectives described in the DoA are three, and they are all are being achieved satisfactorily. In fact, we can state QUARC has become a focal point in Europe in the area of PQC and has spun different activities that expand beyond the core of QUARC. In the following lines we will present the three objectives; we will first provide an overview of how they are being achieved, and on the following section describing the work conducted within the WPs, a more detailed technical description is provided.
O1- To investigate and develop an integral understanding of PQC encryption and how to translate it to a micro-architecture suitable for hardware implementation
This objective is being achieved. The following aspects have been reached during the current reporting period:
• In-depth study of the different PQC algorithms and their building blocks
• Identification of suitable HW platforms for PQC implementation
• Transfer of PQC-algos into single-thread implementation codes for CPUs
• Initial work on transfer of PQC-algos into multi-thread implementation codes for GPUs
O2- To propose PQC implementations exploiting reconfigurable processors and yielding compatibility with existing networking solutions
This objective is being achieved. All implementations proposed in QUARC have been done employing commercially available reconfigurable processors, which can be used by any researcher worldwide. The following aspects have been reached during the current reporting period:
• Implementation of all standardized PQC algorithms on an onboard CPU for a line-rate network interface card
• Implementation of all standardized PQC algorithms employing ARM-based hardware accelerators as HW offloads in a line-rate network interface card
• Implementation of Kyber/Dilithium on a IoT processor unit (i.e. Jetson) at low speed (~1 Gbit/s)
At the moment of this report, the team has started working on converged cards, where ARM-based and GPU-based processors co-exists on the same network interface card.
O3- To develop high-speed PQC demonstrators highlighting the feasibility of in-line encryption resistant to quantum processors
This objective is being achieved. Some of the proposed implementations (See Objective 2) have been ported to high-speed demonstrators. The following aspects have been reached during the current reporting period:
• Demonstration of all PQC algorithms operating at ~100 Gbit/s
• Preliminary design of building block optimizations for ~200 Gbit/s operation
• Preliminary work on GPU off-loading for high-speed PQC operation
We all objectives set in the description of work will be achieved and extend the state-of-the-art in the scientific domain dramatically. As per periodic report 1, the results reported by QUARC have set the global benchmark in the field.
• In-depth study of the different PQC algorithms and their building blocks
• Identification of suitable HW platforms for PQC implementation
• Transfer of PQC-algos into single-thread implementation codes for CPUs
• Initial work on transfer of PQC-algos into multi-thread implementation codes for GPUs
• Implementation of all standardized PQC algorithms on an onboard CPU for a line-rate network interface card
• Implementation of all standardized PQC algorithms employing ARM-based hardware accelerators as HW offloads in a line-rate network interface card
• Implementation of Kyber/Dilithium on a IoT processor unit (i.e. Jetson) at low speed (~1 Gbit/s)
• Demonstration of all PQC algorithms operating at ~100 Gbit/s
• Preliminary design of building block optimizations for ~200 Gbit/s operation
• Preliminary work on GPU off-loading for high-speed PQC operation
• Identification of suitable HW platforms for PQC implementation
• Transfer of PQC-algos into single-thread implementation codes for CPUs
• Initial work on transfer of PQC-algos into multi-thread implementation codes for GPUs
• Implementation of all standardized PQC algorithms on an onboard CPU for a line-rate network interface card
• Implementation of all standardized PQC algorithms employing ARM-based hardware accelerators as HW offloads in a line-rate network interface card
• Implementation of Kyber/Dilithium on a IoT processor unit (i.e. Jetson) at low speed (~1 Gbit/s)
• Demonstration of all PQC algorithms operating at ~100 Gbit/s
• Preliminary design of building block optimizations for ~200 Gbit/s operation
• Preliminary work on GPU off-loading for high-speed PQC operation
QUARC has generated results beyond the state-of-the-art in terms of achieved line-rate.
This has been achieved thanks for hardware optimization and hardware offloading, reconfigurable programming and co-integration of the network stack.
During PR2, we will evaluate the next steps towards co-integration through demonstrations.
This has been achieved thanks for hardware optimization and hardware offloading, reconfigurable programming and co-integration of the network stack.
During PR2, we will evaluate the next steps towards co-integration through demonstrations.