WP2: 2.1 and D2.2 have been submitted at M15 and revised following the review results of PR1. In this Period, a multi-physics model of the SiC power modules has been developed based on HE inputs and module characterization from VUB (incl. double-pulse testing). This high-fidelity model builds towards digital twin of the power module and the converter-level model to be used in WP5. Further, physics-of-failure mechanisms were developed to improve the equipment lifetime and function safety. D2.2 is due by M33 (June 2025); preparation is ongoing.
WP3: The development of SiC MOSFETs and modules led to several key achievements:
1. High-k Gate Oxides: New high-k layers and double high-k layer stacks were developed, enhancing device capacitance and reliability.
2. MOSFET Testing: Fifteen single-chip substrates showed promising threshold and Rdson values.
3. SmartSiCTM Modules: Twenty modules were built and tested, demonstrating low leakage current and reliable blocking capability.
4. Gate Driver Development: Achieved a 30% reduction in cost and size, with improved short-circuit withstand time.
5. SmartSiCTM Gen II SiC-Based Power Modules: Improved edge exclusion and defectivity in SmartSiC Gen II wafers.
WP4: WP4 aims at demonstrating the power-modules and gate-drivers developed in WP3 in a functioning live size test. This is achieved by integrating the delivered HW artifacts into a Power Stack, similar to PWC's current setup, but with voltage increased by 1.8 times to stay within HE’s recommendations for the power modules. Integration of the gate-driver to the control system has been achieved as well as preparations of the interface towards the edge device and IoT. The architecture of the IoT and condition-monitoring features have been established, and the functionality is presently being developed. The IoT system will enable and support the verification of the models developed in WP2.
WP5: Digital modelling of DAB converter and MMC with closed-loop control system has been completed. Therefore, the voltage and current waveforms during dynamic and steady state can be generated. In addition, loss-thermal calculations have been added to the digital model, and thus, the power losses and junction temperature of power semiconductors can be obtained. The high-fidelity MOSFET model has been integrated into the model of the DAB converter, and is currently being integrated into the MMC.
WP6: The methodology of the LCA analysis was defined in coherence with the structure of the project and with the techno economic KPIs
WP7: Communication and exploitation activities will be mentioned in another section.
WP8: Materialized risks have been handled promptly, and proper mitigation measures, including an amendment, have been implemented to ensure viability of the project.
