Periodic Reporting for period 2 - SiC4GRID (NEXT GENERATION MODULAR SIC-BASED ADVANCED POWER ELECTRONICS CONVERTERS FOR ENHANCED RENEWABLES INTEGRATION INTO THE GRID)
Período documentado: 2023-12-01 hasta 2025-05-31
SiC4GRID aims at tackling current obstacles to the SiC technologies' market uptake, addressing both techno-economic and environmental pillars. The consortium will design, produce, test and validate an integrated product composed of a 30% smaller size energy-efficient SiC-based power module. An integrated modular converter will be tested on a physical test bench, as well as digitally to increase the variety of relevant applications and real-condition scenario, considering both wind and solar applications with storage. Overall, the project contributes to advancing the market readiness of the technology by lowering its cost, its size, and increasing its lifetime and its environmental impact.
WP2: 2.1 and D2.2 have been submitted at M15 and revised following the review results of PR1. In this Period, a multi-physics model of the SiC power modules has been developed based on HE inputs and module characterization from VUB (incl. double-pulse testing). This high-fidelity model builds towards digital twin of the power module and the converter-level model to be used in WP5. Further, physics-of-failure mechanisms were developed to improve the equipment lifetime and function safety. D2.2 is due by M33 (June 2025); preparation is ongoing.
WP3: The development of SiC MOSFETs and modules led to several key achievements:
1. High-k Gate Oxides: New high-k layers and double high-k layer stacks were developed, enhancing device capacitance and reliability.
2. MOSFET Testing: Fifteen single-chip substrates showed promising threshold and Rdson values.
3. SmartSiCTM Modules: Twenty modules were built and tested, demonstrating low leakage current and reliable blocking capability.
4. Gate Driver Development: Achieved a 30% reduction in cost and size, with improved short-circuit withstand time.
5. SmartSiCTM Gen II SiC-Based Power Modules: Improved edge exclusion and defectivity in SmartSiC Gen II wafers.
WP4: WP4 aims at demonstrating the power-modules and gate-drivers developed in WP3 in a functioning live size test. This is achieved by integrating the delivered HW artifacts into a Power Stack, similar to PWC's current setup, but with voltage increased by 1.8 times to stay within HE’s recommendations for the power modules. Integration of the gate-driver to the control system has been achieved as well as preparations of the interface towards the edge device and IoT. The architecture of the IoT and condition-monitoring features have been established, and the functionality is presently being developed. The IoT system will enable and support the verification of the models developed in WP2.
WP5: Digital modelling of DAB converter and MMC with closed-loop control system has been completed. Therefore, the voltage and current waveforms during dynamic and steady state can be generated. In addition, loss-thermal calculations have been added to the digital model, and thus, the power losses and junction temperature of power semiconductors can be obtained. The high-fidelity MOSFET model has been integrated into the model of the DAB converter, and is currently being integrated into the MMC.
WP6: The methodology of the LCA analysis was defined in coherence with the structure of the project and with the techno economic KPIs
WP7: Communication and exploitation activities will be mentioned in another section.
WP8: Materialized risks have been handled promptly, and proper mitigation measures, including an amendment, have been implemented to ensure viability of the project.
WP3: The development of SiC MOSFETs and modules led to several key achievements:
1. High-k Gate Oxides: New high-k layers and double high-k layer stacks were developed, enhancing device capacitance and reliability.
2. MOSFET Testing: Fifteen single-chip substrates showed promising threshold and Rdson values.
3. SmartSiCTM Modules: Twenty modules were built and tested, demonstrating low leakage current and reliable blocking capability.
4. Gate Driver Development: Achieved a 30% reduction in cost and size, with improved short-circuit withstand time.
5. SmartSiCTM Gen II SiC-Based Power Modules: Improved edge exclusion and defectivity in SmartSiC Gen II wafers.
WP4: WP4 aims at demonstrating the power-modules and gate-drivers developed in WP3 in a functioning live size test. This is achieved by integrating the delivered HW artifacts into a Power Stack, similar to PWC's current setup, but with voltage increased by 1.8 times to stay within HE’s recommendations for the power modules. Integration of the gate-driver to the control system has been achieved as well as preparations of the interface towards the edge device and IoT. The architecture of the IoT and condition-monitoring features have been established, and the functionality is presently being developed. The IoT system will enable and support the verification of the models developed in WP2.
WP5: Digital modelling of DAB converter and MMC with closed-loop control system has been completed. Therefore, the voltage and current waveforms during dynamic and steady state can be generated. In addition, loss-thermal calculations have been added to the digital model, and thus, the power losses and junction temperature of power semiconductors can be obtained. The high-fidelity MOSFET model has been integrated into the model of the DAB converter, and is currently being integrated into the MMC.
WP6: The methodology of the LCA analysis was defined in coherence with the structure of the project and with the techno economic KPIs
WP7: Communication and exploitation activities will be mentioned in another section.
WP8: Materialized risks have been handled promptly, and proper mitigation measures, including an amendment, have been implemented to ensure viability of the project.
WP2: Multi-physics digital twin modelling of SiC power modules incl. data-driven validation: further research activities for AAU in SiC power modules modelling.
Physics-of-failure mechanisms: VUB will use this for developing research activities and industrial collaborations in SiC power devices reliability and testing.
WP3: The development of SiC MOSFETs and modules led to advancements in high-k gate oxides, MOSFET processing, SmartSiCTM modules, gate driver development, and Gen II SiC-based power modules. These improvements enhance device performance, reliability, and integration into power modules.
WP4: Design of a SmartSiC based MMC power stack exploiting the increased voltage capability of the newly developed power modules. Design of IoT architecture supporting the extraction of vital reliability data from the power modules via the gate-driver and the MMC control system.
WP5: The digital model of converters (DAB and MMC) with loss-thermal calculations provides a simulation tool to predict the converter performance, enabling efficiency- and reliability-oriented design. As an explicit discrete-time model of power electronic converters is derived, the calculation speed can be significantly accelerated, and thus the design efficiency can be improved.
Physics-of-failure mechanisms: VUB will use this for developing research activities and industrial collaborations in SiC power devices reliability and testing.
WP3: The development of SiC MOSFETs and modules led to advancements in high-k gate oxides, MOSFET processing, SmartSiCTM modules, gate driver development, and Gen II SiC-based power modules. These improvements enhance device performance, reliability, and integration into power modules.
WP4: Design of a SmartSiC based MMC power stack exploiting the increased voltage capability of the newly developed power modules. Design of IoT architecture supporting the extraction of vital reliability data from the power modules via the gate-driver and the MMC control system.
WP5: The digital model of converters (DAB and MMC) with loss-thermal calculations provides a simulation tool to predict the converter performance, enabling efficiency- and reliability-oriented design. As an explicit discrete-time model of power electronic converters is derived, the calculation speed can be significantly accelerated, and thus the design efficiency can be improved.