Periodic Reporting for period 1 - SCOPS (Scallable COntroller for Power Sources)
Reporting period: 2023-01-01 to 2024-06-30
To face the increased needs on current consumptions, some new technologies are introduced in power conversion stages (mainly owing to the introduction of GaN transistors). Few years ago, the Si Transistors as switches was the device limiting the performance and the market was dominated by US manufacturers in a monopoly for space application with high costs (need of specific design and foundries to face the radiation environment). This also lead to EU dependence to US export control restrictions. The introduction of GaN transistors allow to get better performances and also EU non dependence as some initiative promote European supply chain (as shown in H2020 EleGaNt ongoing project).
But now, the main integration & performance limitation is now the controller of the power stages available in the market:
- Performance: limited switching frequency operation due to:
*Device technology : most of them in the market are in bipolar technology (slow & power consumption).
*Radiation sensitivity : heavy ions can cause transients that are to be filtered (slowing down the performances).
*Power consumption of the controller itself.
- Functionality: Many functions are set owing to external parts (fine analog tuning, switching...).
This project sets one clear and measurable main objective: To design and evaluate the performance in space environment of Application Specific Integrated Circuit, nameds SCOPS, to control several power supply phases in parallel, using non-dependent supply chain. To do so, it is necessary that SCOPS provides the Space Community with:
- A flexible SCOPS Circuit that overcomes the limitations of existing controllers in terms of phase paralleling possibilities,performance, feature and radiation robustness.
- A fair commercialization and intellectual property management to allow the purchase of the SCOPS outcomes at a competitive cost in front of its non-European alternatives for space applications.
But now, the main integration & performance limitation is now the controller of the power stages available in the market:
- Performance: limited switching frequency operation due to:
*Device technology : most of them in the market are in bipolar technology (slow & power consumption).
*Radiation sensitivity : heavy ions can cause transients that are to be filtered (slowing down the performances).
*Power consumption of the controller itself.
- Functionality: Many functions are set owing to external parts (fine analog tuning, switching...).
This project sets one clear and measurable main objective: To design and evaluate the performance in space environment of Application Specific Integrated Circuit, nameds SCOPS, to control several power supply phases in parallel, using non-dependent supply chain. To do so, it is necessary that SCOPS provides the Space Community with:
- A flexible SCOPS Circuit that overcomes the limitations of existing controllers in terms of phase paralleling possibilities,performance, feature and radiation robustness.
- A fair commercialization and intellectual property management to allow the purchase of the SCOPS outcomes at a competitive cost in front of its non-European alternatives for space applications.
Current status and achievements of the project :
- The PROMISE Design standard and Interface standard have been updated using PROMISE project Return Of Experience and the related application matrix to SCOPS project have been issued. The preliminary specification of the SCOPS circuit have been issued and its consistency with the preliminary test plan (electrical and radiation) verified. The related deliverables have been issued (D2.1 to D2.4).
- The WP2 (SCOPS Circuit Requirement Specification) activities are finished.
- An agreement has been concluded for the licensing of the patent with NXP and INPT ; it is implemented inside the Consortium Agreement (under final signature by the partners). Weekly work sessions were dedicated to the transfer of the patent know-how from INPT to TASF ; in parallel, the architecture of the circuit was refined up to the issuing of the architecture report (D3.2).
- A behavioral model of the circuit was designed and is functional by December 2023. The behavioral model is intensively used to allowed to simulate the global behavior and improved significantly the architecture convergence. TASF validated the circuit and sub blocks main specification using the behavioral model (DC gain, offset, bandwidth, etc…) and dedicated model parameters.
- The circuit detailed specification (D3.3) has been issued and its consistency with the updated test plan (D3.1) (electrical and radiation) verified. 100% of the sub-blocks specifications are finalized. The package footprint BGA81 has been selected with SYNC partner. The Detailed SRR and ADR reviews of the circuit have been held with the consortium and related MoM issued (D3.4 and D3.5).
- The WP3 (SCOPS Circuit Architecture Design) activities are finished.
- The WP4 (SCOPS Circuit Design) is on-going.
- The Circuit Package specification D4.2 have been delivered : the chip padring definition and pinout in accordance with the selected package are defined.
- TASF is finalizing the circuit floorplanning and Top level simulation strategy is under construction based on the behavioral model.
- In parallel, TASF and ISDG are designing the sub-blocks (analogs and 1 digital) based on the specification created during architecture analysis.
- The progress status is : 99% of the architecture design, 79% of schematic simulated, 60% of layout, 55% of the post-layout simulation and 73% of reviews (SRR, ADR, PDR, DDR and CDR).
Next steps :
- The main next steps will be the sub-blocks and the circuit top level design respectively by ISDG and TASF.
- SYNC is designing the BGA81 package.
- Circuit CDR is expected by Q1 2025 and prototypes (package manufacturing + foundry + assembly) are expected by Q3 2025
- The related hardware and software for test will be designed and available as soon as the prototypes are available. Test campaign will be conducted during Q4 2025-Q1 2026 and HTOL will be conducted during H1 2026.
- The PROMISE Design standard and Interface standard have been updated using PROMISE project Return Of Experience and the related application matrix to SCOPS project have been issued. The preliminary specification of the SCOPS circuit have been issued and its consistency with the preliminary test plan (electrical and radiation) verified. The related deliverables have been issued (D2.1 to D2.4).
- The WP2 (SCOPS Circuit Requirement Specification) activities are finished.
- An agreement has been concluded for the licensing of the patent with NXP and INPT ; it is implemented inside the Consortium Agreement (under final signature by the partners). Weekly work sessions were dedicated to the transfer of the patent know-how from INPT to TASF ; in parallel, the architecture of the circuit was refined up to the issuing of the architecture report (D3.2).
- A behavioral model of the circuit was designed and is functional by December 2023. The behavioral model is intensively used to allowed to simulate the global behavior and improved significantly the architecture convergence. TASF validated the circuit and sub blocks main specification using the behavioral model (DC gain, offset, bandwidth, etc…) and dedicated model parameters.
- The circuit detailed specification (D3.3) has been issued and its consistency with the updated test plan (D3.1) (electrical and radiation) verified. 100% of the sub-blocks specifications are finalized. The package footprint BGA81 has been selected with SYNC partner. The Detailed SRR and ADR reviews of the circuit have been held with the consortium and related MoM issued (D3.4 and D3.5).
- The WP3 (SCOPS Circuit Architecture Design) activities are finished.
- The WP4 (SCOPS Circuit Design) is on-going.
- The Circuit Package specification D4.2 have been delivered : the chip padring definition and pinout in accordance with the selected package are defined.
- TASF is finalizing the circuit floorplanning and Top level simulation strategy is under construction based on the behavioral model.
- In parallel, TASF and ISDG are designing the sub-blocks (analogs and 1 digital) based on the specification created during architecture analysis.
- The progress status is : 99% of the architecture design, 79% of schematic simulated, 60% of layout, 55% of the post-layout simulation and 73% of reviews (SRR, ADR, PDR, DDR and CDR).
Next steps :
- The main next steps will be the sub-blocks and the circuit top level design respectively by ISDG and TASF.
- SYNC is designing the BGA81 package.
- Circuit CDR is expected by Q1 2025 and prototypes (package manufacturing + foundry + assembly) are expected by Q3 2025
- The related hardware and software for test will be designed and available as soon as the prototypes are available. Test campaign will be conducted during Q4 2025-Q1 2026 and HTOL will be conducted during H1 2026.
The following images (attached in the section below) are presenting the circuit floorplan, preliminary package definition and significant simulation results:
- Digital sub-block floorplan (image 1)
- Circuit floorplan and padring (image 2)
- Preliminary package definition (image 3)
- System start with 8 phases with 5% VCO impairement (using a behavioral models) (image 4)
- Simulation with 4 converters (image 5):
- T=0 ms : The system starts with 4 converters (empty load).
- T=13 ms : The active load sources 100A.
- T=20 ms : The converter 4 is disabled.
- T=25 ms : The converter 4 is once again enabled.
- Digital sub-block floorplan (image 1)
- Circuit floorplan and padring (image 2)
- Preliminary package definition (image 3)
- System start with 8 phases with 5% VCO impairement (using a behavioral models) (image 4)
- Simulation with 4 converters (image 5):
- T=0 ms : The system starts with 4 converters (empty load).
- T=13 ms : The active load sources 100A.
- T=20 ms : The converter 4 is disabled.
- T=25 ms : The converter 4 is once again enabled.