To date, we have established the full experimental platform required to realize the project’s objectives. We designed and fabricated dedicated NaviGate microstructured chips to host twisted micron-scale graphene heterostructures. These chips integrate a global backgate for electrostatic gating and biasing, together with micron-scale navigation markers. This architecture enables rapid and reliable localization of the twisted devices with the STM tip in the tunneling regime, the application of gate and bias voltages, and the systematic calibration of tip apexes for STM/STS measurements. In parallel, we set up a dedicated nanofabrication laboratory for twisted graphene heterostructures, including the design of the lab space and the purchase and installation of key equipment. The lab was fully installed and became operational in summer 2024. In addition, we designed the ultra-quiet STM room in the new DIPC experimental building to host the mK-STM, imposing stringent requirements on acoustic noise (< 35 dB), electromagnetic fields (< 20 nT) and mechanical vibrations (< 500 nm/s), thus ensuring noise-free, high-resolution STM/STS measurements beyond current standards.
On the instrumentation side, we completed the custom design, installation and setup of a mK-UHV-STM system. The system operates at base temperatures down to 19 mK in ultra-high vacuum conditions, and is optimized for atomic-resolution imaging and spectroscopy of micron-sized twisted graphene moiré devices under electrostatic gating and vector magnetic fields. Particular effort has been devoted to minimizing RF noise to reach an energy resolution of 15 µeV, which is essential for the project’s scientific goals. In parallel, we devoted substantial effort to the optimized fabrication of our own twisted graphene devices (bilayer, trilayer and tetralayer). Over more than one year, we systematically compared fabrication recipes, substrates and chemical treatments, and evaluated device quality and cleanliness using optical microscopy, AFM, Raman spectroscopy and room-temperature STM. As a result, we now routinely produce high-quality twisted graphene heterostructures integrated onto gateable NaviGate chips, providing a robust and reproducible device base for the forthcoming mK-STM studies