igzO-based smaRt Interposer technologieS fOr iNtegrated circuits and pixels

Informations projet

Orison

N° de convention de subvention: 101088591

DOI

10.3030/101088591

Date de signature de la CE 3 Mars 2023

Date de début 1 Mai 2023

Date de fin 30 Avril 2028

Financé au titre de

• European Research Council (ERC)

Coût total

€ 1 999 688,00

Contribution de l’UE

€ 1 999 688,00

Coordonné par

KATHOLIEKE UNIVERSITEIT LEUVEN
Belgium

Periodic Reporting for period 1 - Orison (igzO-based smaRt Interposer technologieS fOr iNtegrated circuits and pixels)

Période du rapport: 2023-05-01 au 2025-10-31

Résumé du contexte et des objectifs généraux du projet

Silicon complementary metal-oxide semiconductor (Si CMOS) technologies are ubiquitous in a plethora of products today employing a multitude of chips. The current challenges of Si chips research and applications are area, power consumption and high-voltage interposing for AR/VR, low-power IoT, high-voltage sensors and actuator interfaces such as MEMS and lab-on-chip.

ORISON’s goal is to develop a scalable toolbox on top of Si CMOS chip technologies for disruptive research activities in ultralow power circuit design, high-voltage interfacing and low-area 3D stacked hybrid pixel engines. The technology platform focuses on a 3D hetero-integration route of Si CMOS and Indium-Gallium-Zinc-Oxide (IGZO) n-type transistors with a 100x lower electron mobility. The game changing nature of ORISON enables innovation on three major pillars: (1) extreme low off-stage leakage currents due to the wide bandgap semiconductor, leading to ultralow power and long retention electronic circuits, (2) the absence of a bulk for IGZO devices, enabling low footprint and high-voltage devices on top of Si CMOS and (3) a 3D technology platform facilitating beyond state-of-the-art circuit and pixel resolutions.

A new hybrid Si pMOS/IGZO cell library will be pioneered targeting ultra-low power consumption because of comparable subthreshold slopes of both technologies, low off-state leakage currents and individual tuneable threshold voltages by a local backgate. In addition, true cell-level power gating techniques are envisioned to radically reduce the idle power consumption, paving the way to lifetime battery-powered or battery-less wearables and leaf-node IoT. The novel high-voltage hybrid library impacts positively MEMS and AR/VR applications with unprecedented footprint and power characteristics and enables technology partitioning for smart pixels. The 3D technology also envisions high-resolution pixel engines with refresh-on-demand capacitor-less pixel engines.

Travail effectué depuis le début du projet jusqu’à la fin de la période considérée dans le rapport et principaux résultats atteints jusqu’à présent

The first period of the project focused primarily on two ambitions. At first to explore the high potential of the novel hybrid 3D monolithically integrated IGZO-Si CMOS technology. We have created a first process design kit and started evaluating the integration options. The first integrated circuits have been designed taking into account the key advantages of the hybrid technology. For IGZO, the main assets are ultralow leakage currents, high voltage interfacing and low area circuitry. A tape out has been performed.

In parallel of the hybrid technology development track, efforts have been directed toward the development of pure IGZO circuits to ensure technological independence and broaden future hybrid CMOS-IGZO applications. We discovered this as a necessary step in order to anticipate sufficient progress during the extensive processing time of such a hybrid technology run. We have been epxloring the option to operate in a foundry-mode model, whereby design groups can focus on the design activity, whereby wafer production is executed by the foundry.

We have studied the IGZO's low leakage currents and applied it to a spiking neural network, achieving a broad frequency range between two spikes, attributed to the advantages of IGZO as a semiconductor.

Progrès au-delà de l’état des connaissances et impact potentiel prévu (y compris l’impact socio-économique et les conséquences sociétales plus larges du projet jusqu’à présent)

One of the project’s key achievements was enabling broader access to advanced manufacturing technologies through a “foundry-mode” model. We are pleased to report that Europractice has now included flexible electronics in its service portfolio, alongside traditional silicon CMOS technologies. This marks a significant step forward in making cutting-edge flexible electronics more accessible to researchers, innovators, and industry.

To ensure the continued uptake and success of this development, targeted training activities will be essential. Our team, including the Principal Investigator and researchers, is actively involved in these efforts. In parallel, identifying and exploring new application areas will be crucial for encouraging industrial adoption and unlocking the full potential of flexible electronics.

Another promising outcome of the project is the development of a neuromorphic circuit based on IGZO (Indium Gallium Zinc Oxide). This technology mimics the way the human brain processes information and holds great promise for future computing systems. However, the current implementation consumes relatively high power due to the use of IGZO-only circuitry. To move forward, further research is needed to explore low-power alternatives. One promising direction is the integration of the ERC-developed hybrid technology, which could significantly improve energy efficiency.