Periodic Reporting for period 1 - SYCLOPS (Scaling extreme analYtics with Cross-architecture acceLeration based on OPen Standards)
Reporting period: 2023-01-01 to 2024-06-30
The vision of SYCLOPS project is to enable better solutions for AI/data mining for extremely large and diverse data by democratizing AI acceleration using open standards, and enabling a healthy, competitive, innovation-driven ecosystem for Europe and beyond. This vision relies on the convergence of two important trends in the industry: (i) the standardization and adoption of RISC-V, an open Instruction Set Architecture (ISA), for AI and analytics acceleration, and (ii) the emergence and growth of SYCL as an open, cross-architecture programming model for all types of accelerators, including RISC-V. The goal of project SYCLOPS is to bring together these standards for the first time in order to (i) demonstrate ground-breaking advances in performance and scalability of extreme data analytics using a standards-based, fully-open, AI acceleration approach, and (ii) enable the development of inter-operable (open and vendor neutral interfaces/APIs), trustworthy (verifiable and standards-based hardware/software), and green (via application-specific processor customization) AI systems.
To achieve these goals, SYCLOPS followed a structured approach made up of four phases: (i) Design and specification, (ii) Research, development, and early prototyping (iii) Scaling up, system enhancements, and complete platform, and (iv) Validation and exploitation.
During the first eighteen months of the project, the consortium first started with the first phase. Given that SYCLOPS involves work on a multi-layered hardware-software stack, the consortium defined clear interfaces between layers to ensure compatibility across layers. The use case partners also performed an analysis of their respective use cases and came up with a specification of benchmarking tools. The result of this work was summarized in deliverable “D2.1: Architecture, interface, and benchmark specification”.
The consortium then moved on to phase two of the project which consisted of three parallel design and implementation activities. At the infrastructure layer of SYCLOPS, we developed v1.0 of the SYCLOPS Edge Data Center (EDC), deployed it at EUR, made it available to all consortium partners, and used it as the basis of demonstrating integration at the interim stage. This platform was described in deliverable “D3.1: EMDC v1.0 with RISC-V platform release”. At the platform layer, the two compilers in SYCLOPS, DPC++ and AdaptiveCPP, were significantly updated to enable SYCL applications to be compiled to RISC-V backends among other functionalities. Consortium partners collaborated on using the oneAPI Construction Kit to enable SYCL kernel execution the RISC-V CPU and FPGA-based soft core. In order to demonstrate successful functioning, at the application level, SYCLDB—a library for hardware accelerated data analytics---was developed. SYCLDB was compiled with both compilers, and the performance of its kernels was evaluated on several backends available in the SYCLOPS EDC, thus demonstrating full integration across all layers of the stack. The result of this work was described in deliverable “D4.1: RISC-V Compiler Backends”. In addition to this work, significant progress has been made on all active tasks, and a detailed updated of per-task activity is provided later in the M18 periodic reporting document.
In summary, the project successfully submitted 9 out of 23 deliverables during the covered period as planned, including technical reports, prototypes, research findings, and dissemination and exploitation strategies. Additionally, 5 out of 10 milestones were achieved ending with the end-to-end verification of relevant parts of the SYCLOPS stack using the EDC V1.0.
During the first eighteen months of the project, the consortium first started with the first phase. Given that SYCLOPS involves work on a multi-layered hardware-software stack, the consortium defined clear interfaces between layers to ensure compatibility across layers. The use case partners also performed an analysis of their respective use cases and came up with a specification of benchmarking tools. The result of this work was summarized in deliverable “D2.1: Architecture, interface, and benchmark specification”.
The consortium then moved on to phase two of the project which consisted of three parallel design and implementation activities. At the infrastructure layer of SYCLOPS, we developed v1.0 of the SYCLOPS Edge Data Center (EDC), deployed it at EUR, made it available to all consortium partners, and used it as the basis of demonstrating integration at the interim stage. This platform was described in deliverable “D3.1: EMDC v1.0 with RISC-V platform release”. At the platform layer, the two compilers in SYCLOPS, DPC++ and AdaptiveCPP, were significantly updated to enable SYCL applications to be compiled to RISC-V backends among other functionalities. Consortium partners collaborated on using the oneAPI Construction Kit to enable SYCL kernel execution the RISC-V CPU and FPGA-based soft core. In order to demonstrate successful functioning, at the application level, SYCLDB—a library for hardware accelerated data analytics---was developed. SYCLDB was compiled with both compilers, and the performance of its kernels was evaluated on several backends available in the SYCLOPS EDC, thus demonstrating full integration across all layers of the stack. The result of this work was described in deliverable “D4.1: RISC-V Compiler Backends”. In addition to this work, significant progress has been made on all active tasks, and a detailed updated of per-task activity is provided later in the M18 periodic reporting document.
In summary, the project successfully submitted 9 out of 23 deliverables during the covered period as planned, including technical reports, prototypes, research findings, and dissemination and exploitation strategies. Additionally, 5 out of 10 milestones were achieved ending with the end-to-end verification of relevant parts of the SYCLOPS stack using the EDC V1.0.
SYCLOPS will advance state-of-the-art on several fronts.
1. Technologies for automated customization of RISC-V accelerators: Based on pioneering research on the design of processor description languages, CSIP has developed codAL, a C-based software language for defining microprocessors. Through SYCLOPS, CSIP has been working on transform codAL and their flagship tool Codasip Studio, into powerful solutions based on the newly proposed RISC-V Vector extensions (RVV) that can be used to develop advanced RISC-V accelerators. Through this, CSIP will be able to target a new high-performance end of the market.
2. SYCL compilers and runtimes. In SYCLOPS, DPC++ and AdaptiveCPP compilers have been extended to support RISC-V, among several ther backends. Support for RISC-V vector extensions is actively being developed. In SYCLOPS, we are also working on transforming Cling into an interactive SYCL interpreter that will enable programmers to develop and execute SYCL code using a Jupyter Notebook frontend for performing ad-hoc data analysis. As notebooks form a key part of the modern-day scientific reproducibility initiatives especially for HPC/data scientists, the SYCL interpreter will provide a major step in bridging the gap between heterogeneous parallelism and reproducible analysis.
3. Profiling tools and performance models. In SYCLOPS, we have customized the CARM tool, an innovative performance profiling tool based on the Cache-Aware Roofline Model, to support RISC-V. We have used the CARM tool to benchmark RISC-V CPUs in our SYCLOPS v1.0 EDC, and various kernels from SYCLOPS application libraries. In addition, in SYCLOPS, we have also developed AdaptivePerf, an open-source low-overhead code profiler for Linux developed with the hardware portability in mind. These profiling tools developed in SYCLOPS will enrich the SYCL an RISC-V developer ecosystem and simplify the task of cross-architecture application development.
4. SYCL libraries. In SYCLOPS, we make two contributions on libraries front. First, we have worked on Syclomatic, an open-source porting tool that can reliably port CUDA code to SYCL, and demonstrated its utility by porting llama.cpp. As our second contribution, we are developing three novel, SYCL-based acceleration libraries, each targeting one of the three use cases: (i) SYCL-DNN for autonomous systems that require analysis of point clouds, (ii) SYCL-ROOT for analysis of data produced by High-Energy Physics experiments, and (iii) SYCL-GAL for accelerating key stages of secondary analysis in computational genomics for precision oncology. The porting tool and libraries developed in SYCLOPS will enrich the SYCL ecosystem and lead to a broader adoption of SYCL for cross-vendor, cross-architecture accelerator programming.
1. Technologies for automated customization of RISC-V accelerators: Based on pioneering research on the design of processor description languages, CSIP has developed codAL, a C-based software language for defining microprocessors. Through SYCLOPS, CSIP has been working on transform codAL and their flagship tool Codasip Studio, into powerful solutions based on the newly proposed RISC-V Vector extensions (RVV) that can be used to develop advanced RISC-V accelerators. Through this, CSIP will be able to target a new high-performance end of the market.
2. SYCL compilers and runtimes. In SYCLOPS, DPC++ and AdaptiveCPP compilers have been extended to support RISC-V, among several ther backends. Support for RISC-V vector extensions is actively being developed. In SYCLOPS, we are also working on transforming Cling into an interactive SYCL interpreter that will enable programmers to develop and execute SYCL code using a Jupyter Notebook frontend for performing ad-hoc data analysis. As notebooks form a key part of the modern-day scientific reproducibility initiatives especially for HPC/data scientists, the SYCL interpreter will provide a major step in bridging the gap between heterogeneous parallelism and reproducible analysis.
3. Profiling tools and performance models. In SYCLOPS, we have customized the CARM tool, an innovative performance profiling tool based on the Cache-Aware Roofline Model, to support RISC-V. We have used the CARM tool to benchmark RISC-V CPUs in our SYCLOPS v1.0 EDC, and various kernels from SYCLOPS application libraries. In addition, in SYCLOPS, we have also developed AdaptivePerf, an open-source low-overhead code profiler for Linux developed with the hardware portability in mind. These profiling tools developed in SYCLOPS will enrich the SYCL an RISC-V developer ecosystem and simplify the task of cross-architecture application development.
4. SYCL libraries. In SYCLOPS, we make two contributions on libraries front. First, we have worked on Syclomatic, an open-source porting tool that can reliably port CUDA code to SYCL, and demonstrated its utility by porting llama.cpp. As our second contribution, we are developing three novel, SYCL-based acceleration libraries, each targeting one of the three use cases: (i) SYCL-DNN for autonomous systems that require analysis of point clouds, (ii) SYCL-ROOT for analysis of data produced by High-Energy Physics experiments, and (iii) SYCL-GAL for accelerating key stages of secondary analysis in computational genomics for precision oncology. The porting tool and libraries developed in SYCLOPS will enrich the SYCL ecosystem and lead to a broader adoption of SYCL for cross-vendor, cross-architecture accelerator programming.