Project description
Democratising hardware acceleration for AI with RISC-V and SYCL
The widespread adoption of AI has resulted in a market for novel hardware accelerators that can efficiently process AI workloads. Unfortunately, all popular AI accelerators today use proprietary hardware-software stacks, leading to a monopolisation of the acceleration market by a few large industry players. The EU-funded SYCLOPS project aims to democratise AI hardware acceleration by building on open standards. On the hardware front, researchers will promote the adoption of RISC-V, an open instruction set architecture based on established reduced instruction set computer (RISC) principles. On the software front, they will promote the adoption of SYCL, an open, cross-vendor, cross-architecture programming model. Standardised, AI acceleration enabled through SYCLOPS is expected to boost performance and scalability of extreme data analytics.
Fields of science
Programme(s)
Funding Scheme
RIA - Research and Innovation actionCoordinator
06410 Biot
France
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Participants (6)
1000 029 Lisboa
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69117 Heidelberg
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1211 Geneve 23
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2273 AB Voorburg
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The organization defined itself as SME (small and medium-sized enterprise) at the time the Grant Agreement was signed.
06600 Antibes
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The organization defined itself as SME (small and medium-sized enterprise) at the time the Grant Agreement was signed.
616 00 Brno
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The organization defined itself as SME (small and medium-sized enterprise) at the time the Grant Agreement was signed.
Partners (1)
M3 5GS Manchester
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The organization defined itself as SME (small and medium-sized enterprise) at the time the Grant Agreement was signed.