Objective 1
The modeling work has developed physical static models for the low-K and high-K dielectric organic thin film transistors OTFTs. The models were then used to develop a full Bayesian inference using for a fully OTFT system. In addition, at the start of the project a machine learning algorithm based on a multi-layer perceptron was developed to model the OTFT devices and used in the circuit modeling. Both low-K and high-K devices exhibit hysteresis in the sub-threshold regime, which is targeted for the circuit operation, complicating the modeling and the circuit design. In addition, the high-K devices exhibit a reverse drain induced barrier lowering. The circuit designs should be robust against these effects. Static OECT compact models have been developed, benchmarked against experimental measurements and used in circuit simulations. The design of the Bayesian inference in OECTs is based on the temporal behavior of the devices and has been realized by device and material design
A neuron based stochastic computing system has been developed and simulated for a complete OTFT system. Data is taken directly from sensors, encoded into probabilities via a circuit and then the probabilities are prepared for the classification using neuron based time encoded streams. The probability is tested using an OTFT stochastic adder but the signals can also be used for the OECT classification system.
Objective 2
The work on the fabrication part of BAYFLEX includes the realization of sensors for EEG measurements, OTFT devices and circuits for the realization of stochastic streams, and OECTs for the classication task. The first protocols for the flexible sensors were developed using polyimide and first evaluations demonstrated the feasibility of EEG recordings. Active OECT sensors were developed and device performance was optimized by varying the device dimensions and exploring the operational regimes. A first evaluation of EEG signals was successful.
Concerning the OTFT manufacturing, an extensive characterization of the low-K dielectric devices was carried out for the device modeling. First circuit designs for the low-k OTFT devices were completed and manufactured. The circuits are currently being evaluated. The process for the high-k devices was developed and measurements were carried out to develop new modeling tools.
Concerning the OECTs, an important materials development has resulted in a process of record (PoR) for fabricating p-type, n-type, and ambipolar OECTs. Detailed characterization was provided for modeling and circuit simulation. cOECTs inverters were realized and demonstrated high operational speed for the classification circuits. The research investigated methods as to how the threshold voltage can be tuned and the robustness of the different materials in the context of a long classification task. Demonstrations of Bayes’ rule using stochastic bitstreams have been realized.
Objective 3
We have identified a suitable classication task for the demonstrator based on sleep stage detection. This classification task would enable a device to improve sleep, which can greatly improve the lives of those suffering from neurodegenerative diseases. In addition, we have explored the possibility of detecting epilepsy using the circuit design from objective 1.
The hardware for the demonstrator involves a challenging integration of the three technologies in objective 2. A process was developed to enable the integration of BAYFLEX technologies on the same substrate. In parallel, a partial integration strategy is also being explored that enables the testing of the different signals on a printed circuit board.
A first life cycle assessment on OTFT and OECT devices was performed. An important part of this process was to develop the LCA inventory, which now includes steps for the fabrication of p-, n- and ambipolar OECTs. The main environmental contributors were found to be photolithography steps and fluorinated resins.
Benchmarking has been carried out to date in two ways. First, a focus has been placed on understanding how well the classification tasks perform via simulations compared to software. Second, a simulated methodology in CMOS has been developed.
