Periodic Reporting for period 1 - AIRHAR (An Energy-Efficient AI Powered Portable Radar System for Human Activity Recognition)
Período documentado: 2023-09-01 hasta 2025-08-31
The project, AIRHAR, addressed the high energy consumption of modern Artificial Intelligence (AI) models, which limits their use in portable, battery-operated devices. Specifically, it focused on Human Activity Recognition (HAR) using radar, a technology that offers privacy-preserving monitoring for applications like ambient assisted living in healthcare, mobile robotics, and indoor security. The project's overall objective was to develop an energy-efficient, AI-powered portable radar system for HAR. The central strategy to achieve this was a hardware-software co-design approach, ensuring that the AI algorithms and the hardware accelerators were developed together to achieve maximum efficiency. The goal was to enable the creation of affordable, battery-powered, and privacy-respecting radar systems.
The project's work progressed across four main objectives, yielding significant technical achievements:
1. Algorithmic Pivot (WP1 & WP2): The project initially investigated novel time-domain feature extraction methods as an alternative to standard spectral analysis (STFT). Experiments showed these new methods either failed to achieve sufficient accuracy or were computationally more expensive than the traditional approach. This key finding led to a strategic pivot. The team shifted its focus from ConvLSTM and Transformer models, which proved too computationally heavy, to a new class of AI called State-Space Models (SSMs).
2. Breakthrough AI Model (RadMamba): The project developed a novel, radar-specific SSM named RadMamba. This model is specifically tailored for micro-Doppler signatures and achieves state-of-the-art accuracy on multiple public datasets.
3. Hardware Co-Design and Validation (WP3): A parallel hardware track validated the co-design methodology. A second, ultra-efficient model named GateCNN was developed specifically for hardware implementation. A functional FPGA (Field-Programmable Gate Array) prototype of this accelerator was successfully built and validated. This hardware prototype demonstrated: (i) Real-time inference: ~107.5 µs per classification; (ii) Ultra-low power: ~15 mW dynamic power; (iii) Extreme efficiency: Used 0% of the FPGA's dedicated DSP or BRAM blocks.
4. System Validation (WP4): While the original plan for a final ASIC (Application-Specific Integrated Circuit) was deferred, the project's core technical goals were fully achieved. The complete hardware-software pipeline was successfully validated using the FPGA prototype and real radar datasets , proving the system's real-time, low-power capabilities.
All major outcomes were disseminated via arXiv preprints and an open-source code repository, embracing Open Science principles.
1. Algorithmic Pivot (WP1 & WP2): The project initially investigated novel time-domain feature extraction methods as an alternative to standard spectral analysis (STFT). Experiments showed these new methods either failed to achieve sufficient accuracy or were computationally more expensive than the traditional approach. This key finding led to a strategic pivot. The team shifted its focus from ConvLSTM and Transformer models, which proved too computationally heavy, to a new class of AI called State-Space Models (SSMs).
2. Breakthrough AI Model (RadMamba): The project developed a novel, radar-specific SSM named RadMamba. This model is specifically tailored for micro-Doppler signatures and achieves state-of-the-art accuracy on multiple public datasets.
3. Hardware Co-Design and Validation (WP3): A parallel hardware track validated the co-design methodology. A second, ultra-efficient model named GateCNN was developed specifically for hardware implementation. A functional FPGA (Field-Programmable Gate Array) prototype of this accelerator was successfully built and validated. This hardware prototype demonstrated: (i) Real-time inference: ~107.5 µs per classification; (ii) Ultra-low power: ~15 mW dynamic power; (iii) Extreme efficiency: Used 0% of the FPGA's dedicated DSP or BRAM blocks.
4. System Validation (WP4): While the original plan for a final ASIC (Application-Specific Integrated Circuit) was deferred, the project's core technical goals were fully achieved. The complete hardware-software pipeline was successfully validated using the FPGA prototype and real radar datasets , proving the system's real-time, low-power capabilities.
All major outcomes were disseminated via arXiv preprints and an open-source code repository, embracing Open Science principles.
The project delivered results that fundamentally push the boundaries of efficient AI for edge devices. The primary breakthrough is the RadMamba algorithm. It delivers state-of-the-art accuracy for radar-based HAR while being 100x to 400x more parameter-efficient than existing Transformer-based methods. This represents an orders-of-magnitude gain in efficiency and fundamentally redefines what is feasible for real-time AI processing on low-power, resource-constrained hardware. Furthermore, the validated GateCNN FPGA prototype serves as a critical proof of concept. By achieving real-time inference at just ~15 mW of dynamic power , the project confirms the technical feasibility of building the affordable, battery-powered, and privacy-preserving radar systems envisioned in the project's objectives. The co-design principles validated in this project are already being applied to other high-impact domains, such as 5G/6G communications.