Periodic Reporting for period 1 - Groove (Germanium quantum processors: more, robust, available)
Reporting period: 2023-06-01 to 2024-05-31
This scaling problem may well be overcome by moving to a semiconductor qubit platform. To date, semiconductor manufacturing technology is the only technology supporting the integration of billions of components onto a single chip. These semiconductor elements are fabricated with an immense precision and consistency, with over 1 trillion components being shipped every year. The integration of billions of transistors on a single chip underpins our current information age. What materials do we need to integrate excellent qubits at large scale for the quantum information age of tomorrow? A semiconductor qubit system may well be the answer and the only feasible way to scale quantum technology to the requisite millions of qubits, while meeting the requirements on feature size and component reproducibility to produce high-yield, high-quality quantum chips. This system provides a clear advantage over current state-of-the-art quantum technologies, where fault-tolerant processors are predicted to take enormous sizes, resulting in a wide range of additional challenges. Moreover, semiconductor qubits can have extremely long coherence times, can be operated with high-fidelity, and can be integrated with classical control electronics. These proof-of-principle operations, together with the decades-long growing investments and resulting technological advances in the semiconductor industry, position semiconductor quantum technology as the designated platform for the fabrication of millions of qubits.
Going beyond few-qubit experiments, in this project we aim to develop a robust framework enabling semiconductor quantum technology to provide a practical quantum advantage. The main objective of Groove is to reproducibly fabricate, test and launch a quantum chip containing 16 high-quality germanium spin qubits. This quantum computer prototype will leverage the small footprint and rapid development of spin qubits in gate-defined quantum dots in combination with the unique properties of the germanium host material. As our research to date has demonstrated promising results for high-quality qubits in germanium, we aim to explore the robustness and scalability that are essential commercialisation. Scientific research often focuses on hero devices and a one-off demonstration of high-fidelity or multi-qubit milestones, with the different state-of-the-art performance metrics (qubit initialization, operation, entanglement, readout) being achieved in a wide variety of devices. However, for commercialisation it is absolutely essential that these quality requirements are consistently achieved in a single device. We strive to make the platform robust by developing high-yield and highly reproducible sample fabrication where all qubits conform to a high minimal fidelity.
More: Develop a 16-qubit germanium quantum processor. To move from the current-generation four-qubit QPUs towards 16-qubit processors, we aim to take a two-step approach where we first fabricate and operate a 10-qubit device, defining the state of the art for spin qubits. Next, taking learnings from this intermediately-sized QPU, we aim to fabricate and operate the 16-qubit device that defines the end goal of this project.
Robust: Ensure the robustness of the design and fabrication process by ensuring high-yield and reproducible chip fabrication with a minimum single-qubit gate fidelity per chip of 99.9% and a minimum two-qubit gate fidelity per chip of 97% (later 99%). To enable robust design and fabrication of the quantum processors, we will take a fundamentally different approach to device fabrication than is being pursued in academic settings. This is reflected in two main domains. Firstly, a large degree of process control. Rather than operating in a hero-device mode, where single working devices are celebrated and focused on, we switch to an operation mode where failing devices are highlighted and singled out, to identify potential issues in the process. Furthermore the process is adapted to minimise the risk of errors and enable early detection of errors, minimising the risk and maximising the output. This is achieved by the development and implementation of a fully automated QPU design framework, that enables parametrised and automated design generation. Furthermore, by implementing well-defined standard operation procedures (SOPs), extensive logging, and regular process control monitoring (PCM), we are able to flag, identify, and resolve potential complications throughout the manufacturing process. All of this enables us to significantly increase device yield, particularly as device sizes are increasing. Secondly, we implement active process optimisation, where we implement short feedback loops between the fabrication, metrology and (quantum) measurements. This allows us to actively optimise the process towards metrics that are relevant to ensure reproducible performance of the QPUs.
Available: Implement an intuitive and user-friendly platform to interact with the qubit chip and perform quantum algorithms. To this end, we will explore collaborations with existing cloud providers and identify the development requirements to connect our QPUs to such platform.