Gradient Clock Synchronization for Networks-on-Chip and Cellular Networks

Project Information

GradeSync

Grant agreement ID: 101123525

DOI

10.3030/101123525

Project closed

EC signature date 19 July 2023

Start date 1 August 2023

End date 30 June 2025

Funded under

• European Research Council (ERC)

Total cost

No data

EU contribution

€ 150 000,00

Coordinated by

CISPA - HELMHOLTZ-ZENTRUM FUR INFORMATIONSSICHERHEIT GGMBH
Germany

Periodic Reporting for period 1 - GradeSync (Gradient Clock Synchronization for Networks-on-Chip and Cellular Networks)

Reporting period: 2023-08-01 to 2025-06-30

Summary of the context and overall objectives of the project

The goal of this project is to demonstrate a novel clock synchronization method, Gradient Clock Synchronization (GCS) in two key application contexts in need of stronger synchronization guarantees:
- Large Systems-on-Chip (SoCs) and Networks-on-Chip (NoCs) do not operate synchronously, despite the relative ease of design and low-latency communication this would offer.
- Despite issues of security and availability, we currently rely on Global Navigation Satellite Systems (GNSS) such as GPS to obtain tightly synchronized time and accurate positioning information. Accurate positioning requires accurate time, explaining why GNSS systems always provide time alongside position.

GradeSync sets out to showcase the potential of GCS by (i) showing that it is practical to perform wireless time offset measurements with relatively simple hardware to an accuracy not too far from what is required for a commercial system and (ii) doing the same for an Application-Specific Integrated Circuit (ASIC) implementation of the GCS algorithm. In both cases, a fully-fledged, optimized, cutting-edge implementation reaching the performance needed for a product is out of reach with the resources allocated to GradeSync. However, we can show that one can get within an order of magnitude of what is required using limited resources, clearly demonstrating the technical feasibility of reaching the performance required for products. Simultaneously, demonstrator implementations and the lessons learned from them reduce the risk involved in more costly, high-effort product development.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

Both demonstrators have been implemented. In the wireless setting, we demonstrated synchronization with an accuracy better than 450 nanoseconds. The implementation can actually achieve an order of magnitude better results, but we were limited by the experimental setup in this context. Moreover, resilience of the method to interference by other signals was shown. This is in line with expectations: essentially, the approach can be viewed as a localized version of a GNSS system, with the benefit of being much more resilient to jamming and interference due to transmitters being much, much closer to the receivers. Moreover, the achieved results confirm that an implementation using dedicated hardware will be able to achieve nanosecond accuracy at reasonable cost and effort.

The ASIC demonstrator and a supporting testboard have been realized, but the time measurement is too inaccurate due to a design issue. However, we could confirm that the system is functional in principle and will perform another fabrication run with adjusted designs. The results obtained so far indicate that the modified ASICs should achieve an estimated synchronization accuracy of 50-250 picoseconds. Given the relatively old process used and the minimalistic design, this will demonstrate that one would be able to achieve accuracy within tens of picosends using a modern process.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

In the wireless setting, the demonstration formed the basis for follow-up pre-commercial development carried out by the spin-off Timelords UG, in the context of a BMBF StartUpSecure project.

The ASIC demonstrator constitutes a novel solution to the task of clock distribution in large-scale synchronous hardware.