Periodic Reporting for period 1 - SPIKEPro (SPIKING PHOTONIC-ELECTRONIC IC FOR QUICK AND EFFICIENT PROCESSING)
Reporting period: 2024-03-01 to 2025-02-28
SPIKEPro’s chip integration approach is based on a common technology platform, connecting ultrafast laser optical neurons with efficient electrical spiking diodes through non-volatile synaptic weights. This enables to simultaneously capitalise on the advantages of both electronics and photonics to deliver efficient and high-speed SNNs going beyond existing implementations. In addition to reducing the energy consumption per spike in the network, SPIKEPro will also develop novel learning strategies and algorithms able to work with reduced number of synaptic connections. These will be possible by exploiting the hardware parameters of the electrical and photonic spiking devices. The outcome of SPIKEPro will have lasting economic, societal and scientific impact. The project will bring ultra-fast and efficient neuromorphic hardware into the disparate fields of edge computing, sensor data processing, high-speed control and computational neuroscience.
Within WP3, we work on the electronic-photonic interconnectivity. The consortium has developed modeling approaches for coupling of electronic and photonic nodes. USTRATH has performed experimental investigation into optical-electrical transitions between spiking nodes and demonstrated basic processing tasks with such. TUI has implemented the electrical spiking model into dynamic simulations of networks for reservoir computing, and has demonstrated good performance for time-series tasks. Pre- and postprocessing methods have been analyzed by TUI and USTRATH, that increase the memory capacity in such networks.
In WP4, USTRATH has investigated experimentally the operation of discrete neurons under multiwavelength optical inputs and in multi-modal regimes of operation. HPE is developing a system-level simulator that is compatible with common ML software frameworks and can connect to SPIKEPro's hardware models.
Within WP5, work has started to prepare measurements for technologies and systems of WPs 2-4. Activities include preliminary development of PCB assembly of chips. Additionally, USTRATH has started early experimental work with discrete devices to verify the processing potential of spiking devices and conducted numerical simulations to study the computational capabilities of networked neurons.