In WP2, which deals with the development of the spiking components, UCL has optimized the fabrication process for the active laser material. With the help of a new annealing technique, we were able to achieve good optical characteristics in the fabricated wafers. UCL and TUE have defined the layer stacks for the electronic and photonic spiking devices and wafers for the electrical devices were successfully grown. TUE has performed simulations and arrived at an initial design of the photonic spiking device whereas the electronic spiking device design is finalized. Memristor process tests have been devised by HPE and TUE.
Within WP3, we work on the electronic-photonic interconnectivity. The consortium has developed modeling approaches for coupling of electronic and photonic nodes. USTRATH has performed experimental investigation into optical-electrical transitions between spiking nodes and demonstrated basic processing tasks with such. TUI has implemented the electrical spiking model into dynamic simulations of networks for reservoir computing, and has demonstrated good performance for time-series tasks. Pre- and postprocessing methods have been analyzed by TUI and USTRATH, that increase the memory capacity in such networks.
In WP4, USTRATH has investigated experimentally the operation of discrete neurons under multiwavelength optical inputs and in multi-modal regimes of operation. HPE is developing a system-level simulator that is compatible with common ML software frameworks and can connect to SPIKEPro's hardware models.
Within WP5, work has started to prepare measurements for technologies and systems of WPs 2-4. Activities include preliminary development of PCB assembly of chips. Additionally, USTRATH has started early experimental work with discrete devices to verify the processing potential of spiking devices and conducted numerical simulations to study the computational capabilities of networked neurons.
