Extensive work has been undertaken so far to reach objectives 1 & 2 with very good progress. The upscale of III-V QCL-epitaxy on 100mm wafers has been achieved by reaching MS2 and MS4 with corresponding deliveries, i.e. D3.1 – “Report on optimized QC heterostructure designs for both wavelength ranges”, D3.2 – “Sixteen 100 mm QCL wafers for operation in the 8 – 10 μm band for Si integration” and D3.3 – “Sixteen 100 mm QCL wafers for operation in the 5.5 – 6.5 μm band for Si integration”. These wafers have been wafer-bonded with very high yield and are currently under processing. MS3 – “Design of QCL laser devices and PICs” has been achieved and D4.1 – “Report on QCL & PIC design” submitted. For the other approach for direct epitaxy on silicon, the work is also on track and the process flow for nanopatterning of silicon wafers has been established and a first patch of nanostructured 8” Si wafers for tests of direct growth on silicon was delivered (D8.1). All work related to the use case demonstrations is on track, too. The deliverables D6.1-D6.4 related to WP 6 – “Use Case demo specification” have been submitted in due time. Deliverables D1.1 – “Project Quality Plan”, D1.2 – “Data Management Plan”, D1.3 – “Progress Report”, D1.4 –“ Riks Assessment Plan”, D9.1 – “Plan for dissemination and exploitation incl. communication activities” and D9.2 – “Updated plan and report on dissemination and exploitation incl. communication activities and intermediate report on standardization” were submitted to the European commission.