Periodic Reporting for period 1 - JOGATE (JOSEPHSON GATED TRANSISTORS AND ELECTRONICS)
Reporting period: 2023-12-01 to 2024-11-30
In JOGATE we utilise the unique superconducting properties in hybrid superconductor-semiconductor components to uncover the mechanisms contributing to the contact resistance and thereby improve it. In doing so, not only we contribute to solving a major obstacle for the energy efficiency of established digital electronics, but we obtain the superconducting analogues to the conventional transistors and diodes. These superconducting components are unique in that they enable new avenues for superconducting circuit design, resulting in opportunities in miniaturisation, performance and cost of devices that find application in communication, sensing and detection, signal amplification and routing.
In JOGATE we wish to study superconducting transistors and diodes and to upgrade their fabrication processes to be compatible with the methods of large-scale integration, making it possible for Europe to lead their industrial production. In parallel, we contribute to finding ways of improving their performance, to ease practical adoption and impact in areas ranging from cryogenic electronics to demanding environments such as space applications. Finally, to demonstrate the value of the technology and to deliver important outcomes in the short-term, we develop two prototype devices for cryogenic microwave signal management: a radiofrequency switch and an integrated superconducting qubit control chip.
The first important aspect is ensuring access to multiple fabrication routes towards JoFET and superconducting diode components: here we did find credible directions towards large-scale integration group-IV channels in CEA's SiGe/Ge-Al contacts, already mature enough to be adopted for JOGATE demonstrators, confirmed by extensive simulation and design work led by CUT.
Additionally, silicon channel devices (p-type doping) are explored through CEA's metallic superconducting silicides, finding preliminary proof of high metal-semiconductor transparency, contributing towards reducing contact resistance and dissipation of integrated electronics.
Moreover, n-type doped silicon contacts to higher Tc superconductors are explored through VTT effort, which established relevant building blocks (doping, wet etching, contact interface engineering), and started the first pathfinder fabrication run.
For JoFET and superconducting diodes implemented with III-V heterostructures, UREG not only verified new phenomena and design concepts in circuital design but contributed to standardized characterization method of the components. This framework enabled validation of new fully-EU-grown heterostructures and will be applied to group-IV channel devices developed in the consortium. Finally, JYU has progressed extensively in developing physical theory which is already proving very valuable both in the interpretation of experimental results and seeding new ideas for component/device design.
- metal-semiconductor contacts with high transparency
- next-generation superconducting circuit architectures
- reducing technical requirements for superconducting diodes and transistors
- validate these components in relevant applications
The principal exploitation pathways include:
- standardizing fabrication processes, publishing it through patenting and PDKs
- characterizing and testing these components, publishing relevant scientific articles and whitepapers
- networking with EU tech ecosystem to guide industrial uptake
- identifying commercialization routes, depending on application
- access to continuation funding for research and development at higher TRL