Scalable, ferroelectric based accelerators for energy efficient edge AI

Project Information

Ferro4EdgeAI

Grant agreement ID: 101135656

DOI

10.3030/101135656

EC signature date 25 October 2023

Start date 1 January 2024

End date 31 December 2027

Funded under

• Digital, Industry and Space

Total cost

€ 3 959 917,25

EU contribution

€ 3 750 364,25

Coordinated by

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
France

Periodic Reporting for period 1 - Ferro4EdgeAI (Scalable, ferroelectric based accelerators for energy efficient edge AI)

Reporting period: 2024-01-01 to 2025-06-30

Summary of the context and overall objectives of the project

The project aims to develop an ultra-low power, scalable edge accelerator for edge intelligence. Our innovative solution incorporates a memory-augmented neural network, based on Back End of Line (BEoL) integrated ferroelectric (FE) technology. The consortium partners bring a range of expertise across the entire value chain, from device technology to prototypes and systems simulations. The goal is to maximise the advantages of FE technology, including reliability, durability, high energy efficiency, low latency, and scalability.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

The key performance indicators of each stage of the value chain, from materials, through devices, bitcells, arrays and circuits have been defined and related to one another. This provides us with firm guidelines for the project work. Design and simulations of the accelerator blocks has started. The first wafers with novel FeFET-2 circuits have been produced, novel bitcells for future wafers have been designed and the optimal material properties defined.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

The device at the heart of FerroEdgeAI is a non-volatile memory cell consisting of a ferroelectric capacitor made using hafnium zirconate, wired to a standard CMOS field effect transistor. This device has the enormous advantage of being ultra-low power and, at the same time, allows a non-destructive, fast read of its memory state, whether that be analogue or digital. It can therefore reply to the needs of data intensive, edge intelligence. The consortium has already defined the optimal material parameters and is currently integrating the device into novel circuits

The projected energy gain of ferroelectric accelerator (NV-XBAR) with respect to baseline micro-cont

The ferrolectric memory cell, called FeFET-2, of Ferro4EdgeAI