Periodic Reporting for period 1 - Ferro4EdgeAI (Scalable, ferroelectric based accelerators for energy efficient edge AI)
Reporting period: 2024-01-01 to 2025-06-30
The project aims to develop an ultra-low power, scalable edge accelerator for edge intelligence. Our innovative solution incorporates a memory-augmented neural network, based on Back End of Line (BEoL) integrated ferroelectric (FE) technology. The consortium partners bring a range of expertise across the entire value chain, from device technology to prototypes and systems simulations. The goal is to maximise the advantages of FE technology, including reliability, durability, high energy efficiency, low latency, and scalability.
The key performance indicators of each stage of the value chain, from materials, through devices, bitcells, arrays and circuits have been defined and related to one another. This provides us with firm guidelines for the project work. Design and simulations of the accelerator blocks has started. The first wafers with novel FeFET-2 circuits have been produced, novel bitcells for future wafers have been designed and the optimal material properties defined.
The device at the heart of FerroEdgeAI is a non-volatile memory cell consisting of a ferroelectric capacitor made using hafnium zirconate, wired to a standard CMOS field effect transistor. This device has the enormous advantage of being ultra-low power and, at the same time, allows a non-destructive, fast read of its memory state, whether that be analogue or digital. It can therefore reply to the needs of data intensive, edge intelligence. The consortium has already defined the optimal material parameters and is currently integrating the device into novel circuits