Full qualification, testing and commercial deployment of a unique on-chip memory technology offering the highest-density embedded memory in a standard CMOS process

Project Information

GCRAM

Grant agreement ID: 101187897

DOI

10.3030/101187897

Project closed

EC signature date 5 December 2024

Start date 1 July 2024

End date 30 June 2026

Funded under

• The European Innovation Council (EIC)

Total cost

No data

EU contribution

€ 2 499 999,00

Coordinated by

RAAAM MEMORY TECHNOLOGIES LTD
Israel

Periodic Reporting for period 1 - GCRAM (Full qualification, testing and commercial deployment of a unique on-chip memory technology offering the highest-density embedded memory in a standard CMOS process)

Reporting period: 2024-07-01 to 2024-12-31

Summary of the context and overall objectives of the project

Modern chips in various applications, such as Artificial Intelligence (AI) and Machine Learning (ML), Automotive, 5G, High performance compute in data centers, etc., require ever-growing amounts of on- chip memory (SRAM) to meet the necessary performances under AI workloads. As a result, the amount of SRAM on almost any chip accounts for over 50% of the chip size. Furthermore, Moore’s Law has ended for SRAM, which no longer scales in advanced CMOS process nodes, resulting in larger silicon footprints and significant cost increase for fabrication.

RAAAM‘s GCRAM is the highest density and most cost-effective on-chip memory technology in the semiconductor industry, providing up-to 50% silicon area reduction and up-to 10X reduced power consumption over commodity SRAM, and it is fully compatible with the standard CMOS fabrication flow, requiring no additional process steps or cost. RAAAM‘s patented technology enables the extension of Moore’s Law for on-chip memories and can be used by semiconductor companies as a drop-in replacement for SRAM in their chips. RAAAM‘s GCRAM technology is protected by 13 granted patents, and several more are in the approval process.

Under the EIC program, RAAAM is developing and qualifying the GCRAM technology for leading edge process node, which will become available for any semiconductor company developing their products in their process to replace its on-chip SRAM with GCRAM, leading to significant cost, performance, and power optimizations.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

The activities performed so far include the technology study and device characteristics of a state-of-the-art process technology of a leading foundry. Based on the studied devices characteristics, the company’s GCRAM technology bitcell was implemented in this state-of-the-art process node and full memory system implementation has started. The on-going development of the GCRAM bitcell and memory system indicated significant advantages over commodity memories based on SRAM, including around 40-50% area reduction over high-density SRAM using similar design rules, and significant power advantages at similar performance.
In addition, activities to develop a digital test-vehicle to characterize the developed memory system have started and proceed according to plan, with the target test-vehicle tape-out planned for April’25.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

Throughout this stage of the project, we have been able to implement the highest-density on-chip memory solution in a state-of-the-art FINFET process technology of a leading foundry, based on our GCRAM solution. The resulting density benefit is up-to 2X compared to commodity high-density SRAM, while also offering significant power benefits.
To further demonstrated and prove this results, a dedicated test-vehicle will be sent for fabrication during Q2/25, and complete silicon characterization will be available during Q4/25.

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