Periodic Reporting for period 1 - QUQUP (QuiX Quantum Universal Quantum Processor)
Reporting period: 2024-11-01 to 2025-10-31
Quantum computing is expected to revolutionize society by tackling computational challenges beyond classical capabilities. Society's reliance on critical-application computing for areas like drug screening, climate prediction, disaster avoidance, and data encryption is growing.
Advancing the digital revolution requires a paradigm shift toward Universal Quantum Computing (UQC) to exponentially accelerate problem-solving capabilities.
QUQUP is to accelerate towards that paradigm by the development of a Universal Quantum Processor (UQP) architecture.
Universal Quantum Computing requires scalable logical qubits. The project objectives are to accelerate the development of an architecture that supports N-qubit entanglement, focused on the quantum processor architecture and its control driver.
To this end, QUQUP will deliver and demonstrate its photonic quantum processor architecture, which includes a fusion network able to generate logical qubits. Deviating from the original approach in demonstrating physical qubits as a preliminary step towards error correction, it has proven more effective to incorporate quantum error correction as a core architectural element from the outset. The solution is to implement logical qubits that natively correct photon-loss errors, making them the fundamental units of a modular, loss-tolerant architecture. By building the system around loss-robust logical qubits and entangling them through configurable fusion networks, the platform allows for scalability and complexity while preserving reliability, enabling truly scalable measurement-based quantum computing. Although this deviates from the original sub-objectives, the main objective and timeline have not changed.
Advancing the digital revolution requires a paradigm shift toward Universal Quantum Computing (UQC) to exponentially accelerate problem-solving capabilities.
QUQUP is to accelerate towards that paradigm by the development of a Universal Quantum Processor (UQP) architecture.
Universal Quantum Computing requires scalable logical qubits. The project objectives are to accelerate the development of an architecture that supports N-qubit entanglement, focused on the quantum processor architecture and its control driver.
To this end, QUQUP will deliver and demonstrate its photonic quantum processor architecture, which includes a fusion network able to generate logical qubits. Deviating from the original approach in demonstrating physical qubits as a preliminary step towards error correction, it has proven more effective to incorporate quantum error correction as a core architectural element from the outset. The solution is to implement logical qubits that natively correct photon-loss errors, making them the fundamental units of a modular, loss-tolerant architecture. By building the system around loss-robust logical qubits and entangling them through configurable fusion networks, the platform allows for scalability and complexity while preserving reliability, enabling truly scalable measurement-based quantum computing. Although this deviates from the original sub-objectives, the main objective and timeline have not changed.
The work is focused on creating a scalable architecture that remains robust despite significant photon loss. This includes evaluating and selecting photonic platforms, designing low-loss components, and implementing logical qubits that correct photon-loss errors as fundamental building blocks. The activities involved were detailed layout design and simulation of photonic structures, the integration of EO materials, the development of custom electronics, and the testing of fusion and switching mechanisms. Two dedicated fabrication runs have been executed to provide the hardware needed to validate the architecture experimentally. Through iterative design, measurement, and refinement, the task advances both the theoretical and practical foundations required for a modular, loss-tolerant photonic quantum processor.
The QUQUP processor architecture is presented as an integral part of the greater UQC system architecture. The PIC design, simulation, and verification process is refined to a closed-loop procedure that ensures the geometries and manufactured results are compliant with system requirements and constraints.
An electronic control and driver unit PACU was developed for controlled operation of core photonic subsystem assemblies, including thermal control, electrical and optical interfacing, and an Ethernet control interface.
The QUQUP processor architecture is presented as an integral part of the greater UQC system architecture. The PIC design, simulation, and verification process is refined to a closed-loop procedure that ensures the geometries and manufactured results are compliant with system requirements and constraints.
An electronic control and driver unit PACU was developed for controlled operation of core photonic subsystem assemblies, including thermal control, electrical and optical interfacing, and an Ethernet control interface.
The work achieved so far stipulates significant progress in the development of a modular, loss-tolerant photonic quantum processor. Key results include the design and simulation of scalable on-chip photonic architectures, integration of electro-optic materials, and development of control and driver electronics compatible with fast feed-forward operation. Two fabrication runs validated low-loss waveguides, crossings, delay lines, and efficient fiber-chip coupling, demonstrating the feasibility of the proposed modular architecture. Fusion networks and switching mechanisms were characterized, confirming the ability for measurement-based quantum computing.
Indicatively, these results have laid out the basis for further system development and refinement. Key needs for successful deployment include further development on hybrid integration and large-scale photonic assembly, demonstration of multi-module systems, and access to pilot fabrication and characterization facilities. Commercialization would benefit from market engagement, intellectual property protection, and international collaboration. Supportive regulatory frameworks and standardization of photonic interfaces will accelerate adoption. Overall, the work provides the basis toward scalable photonic quantum processors and practical applications in computation as well as communication and sensing.
Indicatively, these results have laid out the basis for further system development and refinement. Key needs for successful deployment include further development on hybrid integration and large-scale photonic assembly, demonstration of multi-module systems, and access to pilot fabrication and characterization facilities. Commercialization would benefit from market engagement, intellectual property protection, and international collaboration. Supportive regulatory frameworks and standardization of photonic interfaces will accelerate adoption. Overall, the work provides the basis toward scalable photonic quantum processors and practical applications in computation as well as communication and sensing.