Periodic Reporting for period 1 - QPRINTS (Fault-Tolerant Architectures and Software for Scalable Quantum Computers)
Período documentado: 2025-04-01 hasta 2025-12-31
Quantum computers promise major advances in areas such as materials, chemistry, finance and optimisation, but today’s devices remain highly error-prone. Small imperfections in hardware components and control systems can quickly corrupt computations, making reliable (“fault‑tolerant”) quantum computing a critical bottleneck for the field. This challenge is particularly acute for small and mid‑sized quantum hardware companies, which often lack the resources to build large in‑house fault‑tolerance teams and sophisticated design tools.
The QPRINTS project addresses this gap by developing fault‑tolerant architectures and design software that help quantum hardware developers understand how real‑world imperfections translate into computational errors, and how these errors can be mitigated through tailored error‑correction strategies. The overarching objective is to enable faster, more cost‑effective progress toward scalable, useful quantum computers by providing platform‑tailored architectural “blueprints” and performance “boosts”, together with an end‑to‑end software workflow for design and evaluation.
By strengthening Europe’s capability to design and engineer fault‑tolerant quantum systems across multiple hardware approaches, QPRINTS supports a more competitive and resilient quantum ecosystem, enabling innovators to move from promising prototypes toward practical, large‑scale quantum computing.
The QPRINTS project addresses this gap by developing fault‑tolerant architectures and design software that help quantum hardware developers understand how real‑world imperfections translate into computational errors, and how these errors can be mitigated through tailored error‑correction strategies. The overarching objective is to enable faster, more cost‑effective progress toward scalable, useful quantum computers by providing platform‑tailored architectural “blueprints” and performance “boosts”, together with an end‑to‑end software workflow for design and evaluation.
By strengthening Europe’s capability to design and engineer fault‑tolerant quantum systems across multiple hardware approaches, QPRINTS supports a more competitive and resilient quantum ecosystem, enabling innovators to move from promising prototypes toward practical, large‑scale quantum computing.
During the first reporting period, we developed a full‑stack simulation and analysis workflow to validate fault‑tolerant architectures across the project’s hardware platforms. It links device‑level parameters to logical error rates by combining physical modeling, logical simulation, and architectural constraints.
We have produced five interoperable libraries to model hardware‑specific imperfections. For linear‑optical systems, a tensor‑network simulator for photonic resource‑state generation models photon loss, beam‑splitter imbalance, and phase errors and is used to compute fusion‑network success probabilities and resource‑state fidelity. For matter‑based platforms (trapped ions and spin qubits), a physics‑aware simulator solves time‑dependent Lindblad master equations and outputs Pauli transfer matrices and Kraus operators, converting Hamiltonian controls into discrete error channels for fault‑tolerance analysis.
In the quantum‑ldpc‑sim package, we have consolidated support for LDPC code families such as Bivariate Bicycle, Twisted Torus, and Lifted Product. We have also implemented circuit constructions and logical operations using transversal‑gate methods. The logical‑gates‑sim package generates fault‑tolerant Hadamard and CNOT circuits for planar, rotated, and subsystem surface codes and exports them to standard simulators. Using noise models from the physical simulators, the generated logical circuits were run to produce threshold plots. The results show logical error suppression below physical error rates and provide quantitative benchmarks for the transversal‑gate designs.
We have also implemented a GPU state‑vector simulator in the gpu‑qubit‑sim package. This library supports higher‑dimensional qudits (d≥2) and accelerates simulations relative to CPU baselines, enabling high‑dimensional encoding studies.
We have studied photonic imperfections and found photon loss and mode mismatch to be the dominant imperfections. Analysis shows conventional approaches require <1% loss, while exposure‑based adaptive schemes tolerate up to 18.8% Loss Per Photon Threshold (LPPT), with intermediate thresholds in the 6–10% range. Engineering targets set for quantum‑dot and LNoI platforms: <10% per‑photon loss (conservative) or <6% (aggressive), together with >96% photon indistinguishability (corresponding to the 4% distinguishability threshold). These targets will be used as acceptance criteria for the architectural blueprints.
For optically addressable spin‑1 systems, we mapped platform‑specific non‑idealities (off‑resonant crosstalk, optical‑dipole interactions during readout, and lattice defects) to logical error models. The analysis quantified the density–addressability trade‑off and defined mitigation requirements for surface‑code‑compatible performance.
We have produced five interoperable libraries to model hardware‑specific imperfections. For linear‑optical systems, a tensor‑network simulator for photonic resource‑state generation models photon loss, beam‑splitter imbalance, and phase errors and is used to compute fusion‑network success probabilities and resource‑state fidelity. For matter‑based platforms (trapped ions and spin qubits), a physics‑aware simulator solves time‑dependent Lindblad master equations and outputs Pauli transfer matrices and Kraus operators, converting Hamiltonian controls into discrete error channels for fault‑tolerance analysis.
In the quantum‑ldpc‑sim package, we have consolidated support for LDPC code families such as Bivariate Bicycle, Twisted Torus, and Lifted Product. We have also implemented circuit constructions and logical operations using transversal‑gate methods. The logical‑gates‑sim package generates fault‑tolerant Hadamard and CNOT circuits for planar, rotated, and subsystem surface codes and exports them to standard simulators. Using noise models from the physical simulators, the generated logical circuits were run to produce threshold plots. The results show logical error suppression below physical error rates and provide quantitative benchmarks for the transversal‑gate designs.
We have also implemented a GPU state‑vector simulator in the gpu‑qubit‑sim package. This library supports higher‑dimensional qudits (d≥2) and accelerates simulations relative to CPU baselines, enabling high‑dimensional encoding studies.
We have studied photonic imperfections and found photon loss and mode mismatch to be the dominant imperfections. Analysis shows conventional approaches require <1% loss, while exposure‑based adaptive schemes tolerate up to 18.8% Loss Per Photon Threshold (LPPT), with intermediate thresholds in the 6–10% range. Engineering targets set for quantum‑dot and LNoI platforms: <10% per‑photon loss (conservative) or <6% (aggressive), together with >96% photon indistinguishability (corresponding to the 4% distinguishability threshold). These targets will be used as acceptance criteria for the architectural blueprints.
For optically addressable spin‑1 systems, we mapped platform‑specific non‑idealities (off‑resonant crosstalk, optical‑dipole interactions during readout, and lattice defects) to logical error models. The analysis quantified the density–addressability trade‑off and defined mitigation requirements for surface‑code‑compatible performance.
We have delivered a unified, hardware‑aware simulation and analysis workflow that closes the gap between device‑level imperfections and logical performance. We have integrated physical modeling, high‑performance logical simulation, and architectural synthesis, and we have produced five interoperable libraries that map theoretical parameters to logical threshold data. This has provided end‑to‑end evidence for the project’s target platforms and has anchored engineering targets such as <6% per‑photon loss and >96% photon indistinguishability.
This workflow demonstrates significant reduction in the time needed to evaluate designs by allowing virtual prototyping and by redirecting R&D toward the main performance bottlenecks, for example, loss, mode mismatch, and control errors. We have shown that the LDPC/transversal‑gate approach can lower resource overheads and make results comparable across platforms, which improves confidence for our partners, customers and investors in the ecosystem. To secure adoption and long‑term impact, we need experimental validation against hardware data, strong IPR protection for the key architectural concepts and continued collaboration with manufacturers so designs match real fabrication constraints and can reach the market.
This workflow demonstrates significant reduction in the time needed to evaluate designs by allowing virtual prototyping and by redirecting R&D toward the main performance bottlenecks, for example, loss, mode mismatch, and control errors. We have shown that the LDPC/transversal‑gate approach can lower resource overheads and make results comparable across platforms, which improves confidence for our partners, customers and investors in the ecosystem. To secure adoption and long‑term impact, we need experimental validation against hardware data, strong IPR protection for the key architectural concepts and continued collaboration with manufacturers so designs match real fabrication constraints and can reach the market.