A MILLION QUBIT QUANTUM COMPUTER - HIGHLY SCALABLE SOLID STATE QUANTUM COMPUTING PLATFORM WITH NATIVE OPTICAL NETWORKING

Project Information

QUANTITATIVE

Grant agreement ID: 101188457

DOI

10.3030/101188457

EC signature date 20 November 2024

Start date 1 December 2024

End date 30 November 2026

Funded under

• The European Innovation Council (EIC)

Total cost

No data

EU contribution

€ 2 499 999,00

Coordinated by

QUANTUM TRANSISTORS TECHNOLOGY LTD
Israel

Periodic Reporting for period 1 - QUANTITATIVE (A MILLION QUBIT QUANTUM COMPUTER - HIGHLY SCALABLE SOLID STATE QUANTUM COMPUTINGPLATFORM WITH NATIVE OPTICAL NETWORKING)

Reporting period: 2024-12-01 to 2025-11-30

Summary of the context and overall objectives of the project

The objectives of the QUANTITAIVE project is to lay the foundation for a highly scalable solid state quantum computing platform with native optical networking, which can scale in the future to tens of thousands and hundreds of thousands of qubits quantum computer.
In this project we build the 3 layers of the solution – the multi-qubit layer, the photonic interconnect layer and the control layer, and integrate them together to form a synchronized and highly scalable quantum computing device.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

In the first year of the project, we built the second generation of the qubit and photonic layers, with a target for scalability and manufacturability. The following achievements were reached in this period:
1) Quantum layer – A) An improved design of the qubit elements B) updated PDK for the diamond Fab C) The qubit layer was produced in several cycles in the company’s diamond fab facility and achieved it first year’s target for scalability and manufacturability.
2) Photonic layer – A) improved designs of the photonic layer – including improved alignment with the quantum layer, improved waveguides and improved funcitonalaity of the passive and active building block of the photonic Integrated Circuit (PIC). B) A PDK was developed in the company for manufacturing in a commercial tier 1 Fab. C) The photonic layer was produced in a commercial silicon photonic Fab and has passed the first phase out of three.
3) Control layer – first integration with a 3rd party control platform was achieved

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

The company recently published a paper describing its latest developments which present significant advancements beyond the state of the art. In the paper called
“Highly resilient, error-protected quantum gates in a solid-state quantum network node” the company presents for single qubit and two-qubits implemented on solid-state nitrogen-vacancy (NV) center in diamond an improvement of error per gate by a factor of 9, corresponding to a fidelity of 99.9988%.
These results establish a new state-of-the-art benchmark and demonstrate that NV centers can support gate fidelities competitive with leading superconducting and trapped-ion platforms while offering unique advantages for quantum networking, including optical connectivity and long-lived nuclear memories.

Here is the overview of the results:
High-fidelity quantum gates are a cornerstone of any quantum computing and communications architecture. Realizing such control in the presence of realistic errors at the level required for beyond-threshold quantum error correction is a long-standing challenge for all quantum hardware platforms. Here we theoretically develop and experimentally demonstrate error-protected quantum gates in a solid-state quantum network node. Our work combines room-temperature randomized benchmarking with a new class of composite pulses that are simultaneously robust to frequency and amplitude, affecting random and systematic errors. We introduce Power-Unaffected, Doubly-Detuning-Insensitive Gates (PUDDINGs) - a theoretical framework for constructing conditional gates with immunity to both amplitude and frequency errors. For single-qubit and two-qubit CNOT gate demonstrations in a solid-state nitrogen-vacancy (NV) center in diamond, we systematically measure an improvement in the error per gate up to a factor of 9. By projecting the application of PUDDING to cryogenic temperatures we show a record two-qubit error per gate of 1.2X10-5 , corresponding to a fidelity of 99.9988% , far below the thresholds required by surface and color code error correction. These results present viable building blocks for a new class of fault-tolerant quantum networks and represent the first experimental realization of error-protected conditional gates in solid-state systems.
The full article can be downloaded from the following address:
https://arxiv.org/abs/2512.05322

The effects of the results on the industry:
More broadly, the convergence of precise pulse engineering, detailed noise modeling, and quantitative benchmarking realized in our work marks a significant step toward practical, distributed quantum computing. We expect the ideas introduced in this work to inform the design of robust conditional gates across a wide variety of quantum technologies and to play a central role in the development of scalable, fault-tolerant quantum network architectures.

Quantum Transistors’ multi-qubit computing technology on a chip