Electrostatic Discharge (ESD) is known to be one of the main causes for failures in ULSI technologies. These failures are caused by the discharge of electrostatic charge present either on an external body, like humans or machines, or on the device itself. In order to cope with this problem, ESD protection circuits have to be provided at all input, output and power supply pins, to ensure that the discharge currents are safely conducted towards the ground.With the ever continuing scaling of CMOS technologies , the problem of ESD becomes more and more difficult to cope with. This makes the scaled down technologies more vulnerable to ESD discharges with each new technology generation. Moreover, new materials and technology modules are continuously introduced in future technologies: high k dielectrics and metal gates to replace the conventional SiO2/polySi gate stacks, copper interconnects and low k dielectrics to replace the conventional Al/oxide based interconnect schemes, and new types of devices such as FinFet s are under study to cope with the scaling problems of conventional MOSFET and apos;s. The impact of these new modules and materials on the ESD robustness of the devices is unknown and needs to be investigated.The ESD protection of RF CMOS circuits also po ses severe problems. The reason for this is that the conventional ESD protection elements cannot be used anymore due to the too high parasitics of the protection elements. As a result new devices and/or design approaches to provide ESD protection for RF-CM OS applications are urgently necessary.In this project these important reliability issues for future technologies will be studied. The impact of advanced CMOS process modules, novel SOI-based devices and advanced junctions on the ESD performance of more or less conventional ESD protection devices will be studied in great detail. New ESD protection strategies and design methodologies for RF CMOS circuits will be investigated and developed.
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