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Electrostatic Discharge Protection for Emerging CMOS Technologies and RF Applications

Final Activity Report Summary - ELECTRA (Electrostatic Discharge Protection for Emerging CMOS Technologies and RF Applications)

Electrostatic Discharge (ESD) is known to be one of the main causes for failures in ultra-large scale integration (ULSI) technologies. These failures are caused by the discharge of electrostatic charge present either on an external body, like humans or machines, or on the device itself. In order to cope with this problem, ESD protection circuits have to be provided at all input, output and power supply pins, to ensure that the discharge currents are safely conducted towards the ground. The ever continuing down-scaling makes technologies more vulnerable to ESD discharges with each new generation. Furthermore, new materials will continuously be introduced in future technologies and their impact on ESD robustness is unknown. The impact of advanced complementary metal-oxide semiconductor (CMOS) process modules and novel silicon-on-insulator (SOI) based devices on the ESD performance were studied in detail in this project.

High k dielectrics and metal gates are expected to replace the conventional silicon oxide and polysilicon gate stacks for the 32 nm CMOS node. While a better robustness of new gate stacks would have been expected due to their higher thickness than current ones, only an equivalent robustness was observed. Robustness was shown to be dependent on the stress polarity. This behaviour was analysed and linked to the underlying physics. The work also focused on new types of devices, FinFets, which were under study to cope with the scaling problems of conventional MOSFET's. Active FinFET devices, which could be the core of future high-end computers, were thoroughly analysed through ESD measurement and simulation. Their extreme sensitivity was demonstrated. Technology parameters like uniformity of dopant-atom distribution in the device were identified as key parameters to ensure a reasonable ESD robustness. Possible protection devices that could be integrated in FinFET technology were studied. Diodes were identified as possible protection elements to implement an ESD protection circuitry. Diodes behaviour was analysed as a function of different technology options, such as high-k and metal gate. Overall performances were demonstrated to be dependent on the chosen technology options.

All the results obtained showed that ESD reliability issues were not likely to be a show stopper for future technology. However, they stressed out that circuit design and application with a reasonable robustness is going to be very challenging. In comparison with current commercial technology, more research effort will be needed to provide ESD protection solutions to reach the required robustness level of applications that will use future CMOS technologies.