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Development and Application of a Low-Cost, High-Performance, Multiprocessor Machine

Objective

The objective of SUPERNODE was to develop a high-performance, multiprocessor, prototype computer with a flexible architecture, suitable for a wide range of scientific and engineering problems.
The objective was to develop a high performance, multiprocessor, prototype computer with a flexible architecture, suitable for a wide range of scientific and engineering problems. The basic component (the T800 version of the transputer with a floating point multiplier facility) and the Supernode computer developed in the project are representative of the present state of the art. A 1000 transputer machine was implemented as an array of supernodes. The machine architecture is expandable, and the interconnection of nodes is reconfigurable, as are the transputers at the node level. A high speed input/output interface (100 Mbit/s) was developed for real time vision applications. The basis for software development is OCCAM and the INMOS transputer development system. The software development host is either MSDOS or Unix using the transputer development system with extensions. The target code is downloaded to Supernode over a transputer communications connection. Important applications in signal processing and logic simulation benefiting directly from the parallel processing environment have been successfully developed. Other studies have been made of the user software environments in the following areas: image processing, scientific applications, computer aided design (CAD), ray tracing, computer aided manufacture (CAM), and in the provision of a numerical algorithms library.
Results were as follows:
-Hardware
The basic component (the T800 version of the transputer with a floating-point multiplier facility) and the Supernode computer developed in the project are representative of the present state of the art. A 1000-transputer machine was implemented as an arr ay of supernodes. The machine architecture is expandable, and the interconnection of nodes is reconfigurable, as are the transputers at the node level. A high-speed input/output interface (100 Mbit/s) was developed for real-time vision applications. Further multi-node machines are currently under test prior to delivery.
-Base-level software
The basis for software development is OCCAM and the INMOS transputer development system. The software development host is either MSDOS or Unix using the Transputer Development System with extensions. The target code is downloaded to Supernode over a tran sputer communications connection.
-User software
Important applications in signal processing and logic simulation benefiting directly from the parallel processing environment have been successfully developed. Other studies have been made of the user software environments in the following areas: image p rocessing, scientific applications, CAD, ray tracing, CAM, and in the provision of a numerical algorithms library.
Exploitation
The T800 transputer is a significant industrial result from INMOS and is now manufactured for industrial use. Five hundred designs worldwide are based on the T800 and its spin-offs. Single and multiple node Supernode-based machines are being marketed.Among the applications and products that have resulted from the work packages of this project are the following: the LUCKY-LOG logic simulator in the CAD for VLSI area, now presented as an add-on card for PCs; several image-processing applications; digital signal processing applications; applications of image generation by the ray-tracing method; multi-transputer architecture studies in CAM; the provision of diagnostics and debuggers; and Occam and Fortran libraries.
The Supernode computer has been further developed to the product level by Telmat and Thorn-EMI. A new subsidiary of Thorn-EMI, PARSYS, has been set up to handle the product. Manufacturing of components is shared between the companies to encourage economies of scale.
The project has attracted wide interest in the architectures community, particularly through several international presentations.
The availability of parallel processing hardware, based around systems such as T800, has demonstrated the poor level of software to support such systems. Efforts are in progress to address the shortcomings in both skills and products.

Coordinator

Defence Research Agency (DRA)
Address
St Andrews Road
WR14 3PS Malvern
United Kingdom

Participants (6)

APSIS
France
Address
61 Chemin Du Vieux Chêne
38244 Meylan
Central Research Laboratories plc
United Kingdom
Address
Dawley Road
UB3 1HH Hayes
Inmos Ltd
United Kingdom
Address
1,000 Aztec West
BS12 4SQ Almondsbury
Institut National Polytechnique de Grenoble
France
Address

38402 Saint-martin-d'hères
Telmat Informatique SA
France
Address
6 Rue De L'industrie Zone Industrielle
68360 Soultz
University of Southampton
United Kingdom
Address
Highfield
SO9 5NH Southampton