Objetivo The objective of this project was to develop high density interconnect compatible with one micron MOS and bipolar VLSI technologies. This technology was to feature four levels of low resistivity metal interconnect with high electromigration resistance andstable, low-resistance contacts to the underlying silicon circuit. The objective of this project was to develop high density interconnect compatible with one micron metal oxide semiconductor (MOS) and bipolar very large scale integration (VLSI) technologies. This technology was to feature 4 levels of low resistivity metal interconnect with high electromigration resistance and stable, low resistance contacts to the underlying silicon circuit. The project achieved its overall objectives and demonstrated several advanced new techniques. The main milestones of the programme were:demonstration of 3-layer metal at 5 micron pitch;demonstration of 4-layer metal at 3 micron pitch.The first main milestone was reached and several variants of the developed structures for nonnested vias and pillars were evaluated by means of the final test mask.The fabrication of 100 per cent filled small vias with aluminium alloys was eventually demonstrated. Work on contact systems and tests on the reliability of polyamide and nitride produced very good results.The project achieved its overall objectives and demonstrated several advanced new techniques. The main milestones of the programme were: -demonstration of 3layer metal at 5micron pitch (September1986) -demonstration of 4-layer metal at 3micron pitch (March1987). The first main milestone was reached on time and several variants of the developed structures for non-nested vias and pillars were evaluated by means of the final test mask towards the final milestone. A major technical difficulty was encountered while setting up the final process. Although good progress had been made with optimised aluminium for step coverage, it was discovered that these conditions did not fill small holes such as contacts and vias. The work was therefore restructured and new sub-tasks added in order to reach the final milestone. The fabrication of 100% filled small vias with Al alloys was eventually demonstrated following close collaboration with advanced equipment manufacturers.Work on contact systems and tests on the reliability of polyimide and nitride also produced very good results. Exploitation All the partners make use of the developed interconnect results in their CMOS or bipolar processes. Plessey, notably, has transferred the 3layer metallisation scheme developed to its CMOS process. Ámbito científico ciencias naturalesciencias químicasquímica inorgánicacompuestos inorgánicosciencias naturalesciencias químicasquímica inorgánicametales de postransiciónciencias naturalesciencias físicaselectromagnetismo y electrónicadispositivo semiconductorciencias naturalesciencias químicasquímica inorgánicametaloides Programa(s) FP1-ESPRIT 1 - European programme (EEC) for research and development in information technologies (ESPRIT), 1984-1988 Tema(s) Data not available Convocatoria de propuestas Data not available Régimen de financiación Data not available Coordinador GEC Plessey Semiconductors plc Dirección Caswell NN12 8EQ Towcester Reino Unido Ver en el mapa Aportación de la UE Sin datos Participantes (3) Ordenar alfabéticamente Ordenar por aportación de la UE Ampliar todo Contraer todo GEC-Marconi Materials Technology Ltd Reino Unido Aportación de la UE € 0,00 Dirección Elstree way WD6 1RX Borehamwood Ver en el mapa Otras fuentes de financiación Sin datos Telefunken Microelectronic GmbH Alemania Aportación de la UE € 0,00 Dirección Theresienstraße 2 74072 Heilbronn Ver en el mapa Otras fuentes de financiación Sin datos Thomson CSF Francia Aportación de la UE € 0,00 Dirección 38 rue vauthier 92100 Boulogne-billancourt Ver en el mapa Otras fuentes de financiación Sin datos
